Lines Matching refs:ADDR_FIX_1

387 #define ADDR_FIX_1(x1)			(1 << (x1))  macro
388 #define ADDR_FIX_2(x1, x2)		(ADDR_FIX_1(x1) | ADDR_FIX_1(x2))
389 #define ADDR_FIX_3(x1, x2, x3)		(ADDR_FIX_1(x1) | ADDR_FIX_2(x2, x3))
390 #define ADDR_FIX_4(x1, x2, x3, x4)	(ADDR_FIX_1(x1) | ADDR_FIX_3(x2, x3, x4))
391 #define ADDR_FIX_5(x1, x2, x3, x4, x5)  (ADDR_FIX_1(x1) | ADDR_FIX_4(x2, x3, x4, x5))
2104 		F_LEN_VAR | F_LEN_VAR_FIXED, R_ALL, D_BDW_PLUS, ADDR_FIX_1(2),
2108 		ADDR_FIX_1(1), 10, cmd_handler_mi_store_data_imm},
2120 		F_LEN_VAR | F_LEN_VAR_FIXED, R_ALL, D_ALL, ADDR_FIX_1(2), 8,
2126 	{"MI_CLFLUSH", OP_MI_CLFLUSH, F_LEN_VAR, R_ALL, D_ALL, ADDR_FIX_1(1),
2130 		F_LEN_VAR | F_LEN_VAR_FIXED, R_ALL, D_ALL, ADDR_FIX_1(1), 6,
2134 		F_LEN_VAR | F_LEN_VAR_FIXED, R_ALL, D_ALL, ADDR_FIX_1(2), 8,
2146 		R_RCS, D_ALL, ADDR_FIX_1(2), 8, NULL, CMD_LEN(2)},
2149 		ADDR_FIX_1(2), 8, NULL},
2154 	{"MI_OP_2F", OP_MI_2F, F_LEN_VAR, R_ALL, D_BDW_PLUS, ADDR_FIX_1(1),
2162 		F_LEN_VAR | F_LEN_VAR_FIXED, R_ALL, D_ALL, ADDR_FIX_1(2), 8,
2175 		F_LEN_VAR, R_BCS, D_ALL, ADDR_FIX_1(4), 8, NULL},
2183 		ADDR_FIX_1(3), 8, NULL},
2189 		ADDR_FIX_1(4), 8, NULL},
2195 		ADDR_FIX_1(4), 8, NULL},
2216 		D_ALL, ADDR_FIX_1(4), 8, NULL},
2219 		F_LEN_VAR, R_BCS, D_ALL, ADDR_FIX_1(4), 8, NULL},
2222 		D_ALL, ADDR_FIX_1(4), 8, NULL},
2238 		F_LEN_VAR, R_BCS, D_ALL, ADDR_FIX_1(4), 8, NULL},
2405 		D_BDW_PLUS, ADDR_FIX_1(2), 8, NULL},
2462 		D_ALL, ADDR_FIX_1(2), 8, NULL},
2486 		D_ALL, ADDR_FIX_1(2), 8, NULL},
2489 		R_RCS, D_ALL, ADDR_FIX_1(2), 8, NULL},
2520 		F_LEN_VAR, R_RCS, D_BDW_PLUS, ADDR_FIX_1(1), 8, NULL},
2523 		F_LEN_VAR, R_RCS, D_BDW_PLUS, ADDR_FIX_1(1), 8, NULL},
2527 		F_LEN_VAR, R_RCS, D_BDW_PLUS, ADDR_FIX_1(1), 8, NULL},
2533 		ADDR_FIX_1(2), 8, cmd_handler_pipe_control},
2541 		ADDR_FIX_1(1), 8, NULL},
2549 		ADDR_FIX_1(1), 8, NULL},
2661 		R_VCS, D_ALL, ADDR_FIX_1(2), 12, NULL},