Lines Matching refs:uint32_t
51 uint32_t vmid;
52 uint32_t mc_id;
53 uint32_t status;
64 uint32_t vram_width;
65 uint32_t mem_clk_max;
111 uint32_t num_pipe_per_mec;
114 uint32_t num_queue_per_pipe;
123 uint32_t *sdma_doorbell_idx;
128 uint32_t non_cp_doorbells_start;
129 uint32_t non_cp_doorbells_end;
150 uint32_t *tile_config_ptr;
151 uint32_t *macro_tile_config_ptr;
152 uint32_t num_tile_configs;
153 uint32_t num_macro_tile_configs;
155 uint32_t gb_addr_config;
156 uint32_t num_banks;
157 uint32_t num_ranks;
222 void (*program_sh_mem_settings)(struct amdgpu_device *adev, uint32_t vmid,
223 uint32_t sh_mem_config, uint32_t sh_mem_ape1_base,
224 uint32_t sh_mem_ape1_limit, uint32_t sh_mem_bases,
225 uint32_t inst);
228 unsigned int vmid, uint32_t inst);
230 int (*init_interrupts)(struct amdgpu_device *adev, uint32_t pipe_id,
231 uint32_t inst);
233 int (*hqd_load)(struct amdgpu_device *adev, void *mqd, uint32_t pipe_id,
234 uint32_t queue_id, uint32_t __user *wptr,
235 uint32_t wptr_shift, uint32_t wptr_mask,
236 struct mm_struct *mm, uint32_t inst);
239 uint32_t pipe_id, uint32_t queue_id,
240 uint32_t doorbell_off, uint32_t inst);
243 uint32_t __user *wptr, struct mm_struct *mm);
246 uint32_t pipe_id, uint32_t queue_id,
247 uint32_t (**dump)[2], uint32_t *n_regs, uint32_t inst);
250 uint32_t engine_id, uint32_t queue_id,
251 uint32_t (**dump)[2], uint32_t *n_regs);
254 uint64_t queue_address, uint32_t pipe_id,
255 uint32_t queue_id, uint32_t inst);
259 unsigned int timeout, uint32_t pipe_id,
260 uint32_t queue_id, uint32_t inst);
268 uint32_t gfx_index_val,
269 uint32_t sq_cmd, uint32_t inst);
279 uint64_t va, uint32_t vmid);
282 uint32_t vmid, uint64_t page_table_base);
283 uint32_t (*read_vmid_from_vmfault_reg)(struct amdgpu_device *adev);
285 uint32_t (*enable_debug_trap)(struct amdgpu_device *adev,
287 uint32_t vmid);
288 uint32_t (*disable_debug_trap)(struct amdgpu_device *adev,
290 uint32_t vmid);
292 uint32_t trap_override,
293 uint32_t *trap_mask_supported);
294 uint32_t (*set_wave_launch_trap_override)(struct amdgpu_device *adev,
295 uint32_t vmid,
296 uint32_t trap_override,
297 uint32_t trap_mask_bits,
298 uint32_t trap_mask_request,
299 uint32_t *trap_mask_prev,
300 uint32_t kfd_dbg_trap_cntl_prev);
301 uint32_t (*set_wave_launch_mode)(struct amdgpu_device *adev,
303 uint32_t vmid);
304 uint32_t (*set_address_watch)(struct amdgpu_device *adev,
306 uint32_t watch_address_mask,
307 uint32_t watch_id,
308 uint32_t watch_mode,
309 uint32_t debug_vmid,
310 uint32_t inst);
311 uint32_t (*clear_address_watch)(struct amdgpu_device *adev,
312 uint32_t watch_id);
314 uint32_t *wait_times,
315 uint32_t inst);
317 uint32_t wait_times,
318 uint32_t sch_wave,
319 uint32_t que_sleep,
320 uint32_t *reg_offset,
321 uint32_t *reg_data);
324 int *max_waves_per_cu, uint32_t inst);
326 uint32_t vmid, uint64_t tba_addr, uint64_t tma_addr,
327 uint32_t inst);
329 uint32_t pipe_id, uint32_t queue_id,
330 uint32_t inst);
332 uint32_t pipe_id, uint32_t queue_id,
333 uint32_t inst, unsigned int utimeout);
334 uint32_t (*hqd_sdma_get_doorbell)(struct amdgpu_device *adev,