75 		if (dml2->v20.dml_core_ctx.project != dml_project_dcn35 &&  in map_hw_resources()
76 			dml2->v20.dml_core_ctx.project != dml_project_dcn36 &&  in map_hw_resources()
77 			dml2->v20.dml_core_ctx.project != dml_project_dcn351) {  in map_hw_resources()
87 …dml2->v20.scratch.dml_to_dc_pipe_mapping.dml_pipe_idx_to_stream_id[num_pipes] = dml2->v20.scratch.…  in map_hw_resources()
88 			dml2->v20.scratch.dml_to_dc_pipe_mapping.dml_pipe_idx_to_stream_id_valid[num_pipes] = true;  in map_hw_resources()
89 …dml2->v20.scratch.dml_to_dc_pipe_mapping.dml_pipe_idx_to_plane_id[num_pipes] = dml2->v20.scratch.d…  in map_hw_resources()
90 			dml2->v20.scratch.dml_to_dc_pipe_mapping.dml_pipe_idx_to_plane_id_valid[num_pipes] = true;  in map_hw_resources()
100 	struct dml2_wrapper_scratch *s = &dml2->v20.scratch;  in pack_and_call_dml_mode_support_ex()
102 	s->mode_support_params.mode_lib = &dml2->v20.dml_core_ctx;  in pack_and_call_dml_mode_support_ex()
231 …struct dml2_calculate_lowest_supported_state_for_temp_read_scratch *s = &dml2->v20.scratch.dml2_ca…  in calculate_lowest_supported_state_for_temp_read()
232 	struct dml2_wrapper_scratch *s_global = &dml2->v20.scratch;  in calculate_lowest_supported_state_for_temp_read()
237 	build_unoptimized_policy_settings(dml2->v20.dml_core_ctx.project, &dml2->v20.dml_core_ctx.policy);  in calculate_lowest_supported_state_for_temp_read()
262 	for (i = 0; i < dml2->v20.dml_core_ctx.states.num_states; i++) {  in calculate_lowest_supported_state_for_temp_read()
263 …s->uclk_change_latencies[i] = dml2->v20.dml_core_ctx.states.state_array[i].dram_clock_change_laten…  in calculate_lowest_supported_state_for_temp_read()
267 		for (j = 0; j < dml2->v20.dml_core_ctx.states.num_states; j++) {  in calculate_lowest_supported_state_for_temp_read()
268 …dml2->v20.dml_core_ctx.states.state_array[j].dram_clock_change_latency_us = s_global->dummy_pstate…  in calculate_lowest_supported_state_for_temp_read()
275 …dml_result = dml_mode_programming(&dml2->v20.dml_core_ctx, s_global->mode_support_params.out_lowes…  in calculate_lowest_supported_state_for_temp_read()
279 			dml2_extract_watermark_set(&dml2->v20.g6_temp_read_watermark_set, &dml2->v20.dml_core_ctx);  in calculate_lowest_supported_state_for_temp_read()
280 …dml2->v20.g6_temp_read_watermark_set.cstate_pstate.fclk_pstate_change_ns = dml2->v20.g6_temp_read_…  in calculate_lowest_supported_state_for_temp_read()
284 …while (dml2->v20.dml_core_ctx.states.state_array[result].dram_speed_mts < s_global->dummy_pstate_t…  in calculate_lowest_supported_state_for_temp_read()
291 	for (i = 0; i < dml2->v20.dml_core_ctx.states.num_states; i++) {  in calculate_lowest_supported_state_for_temp_read()
292 …dml2->v20.dml_core_ctx.states.state_array[i].dram_clock_change_latency_us = s->uclk_change_latenci…  in calculate_lowest_supported_state_for_temp_read()
338 	struct dml2_wrapper_scratch *s = &dml2->v20.scratch;  in dml_mode_support_wrapper()
342 	build_unoptimized_policy_settings(dml2->v20.dml_core_ctx.project, &dml2->v20.dml_core_ctx.policy);  in dml_mode_support_wrapper()
379 		s->cur_policy = dml2->v20.dml_core_ctx.policy;  in dml_mode_support_wrapper()
380 		s->optimize_configuration_params.dml_core_ctx = &dml2->v20.dml_core_ctx;  in dml_mode_support_wrapper()
382 		s->optimize_configuration_params.ip_params = &dml2->v20.dml_core_ctx.ip;  in dml_mode_support_wrapper()
390 			dml2->v20.dml_core_ctx.policy = s->new_policy;  in dml_mode_support_wrapper()
404 				dml2->v20.dml_core_ctx.policy = s->cur_policy;  in dml_mode_support_wrapper()
439 	struct dml2_wrapper_scratch *s = &dml2->v20.scratch;  in optimize_pstate_with_svp_and_drr()
466 …result = dml_mode_programming(&dml2->v20.dml_core_ctx, s->mode_support_params.out_lowest_state_idx…  in optimize_pstate_with_svp_and_drr()
544 	struct dml2_wrapper_scratch *s = &dml2->v20.scratch;  in call_dml_mode_support_and_programming()
570 			result = dml_mode_programming(&dml2->v20.dml_core_ctx, min_state, &s->cur_display_config, true);  in call_dml_mode_support_and_programming()
572 …result = dml_mode_programming(&dml2->v20.dml_core_ctx, s->mode_support_params.out_lowest_state_idx…  in call_dml_mode_support_and_programming()
581 	struct dml2_wrapper_scratch *s = &dml2->v20.scratch;  in dml2_validate_and_build_resource()
592 …out_clks.dcfclk_khz = (unsigned int)dml2->v20.dml_core_ctx.states.state_array[lowest_state_idx].dc…  in dml2_validate_and_build_resource()
593 …out_clks.fclk_khz = (unsigned int)dml2->v20.dml_core_ctx.states.state_array[lowest_state_idx].fabr…  in dml2_validate_and_build_resource()
594 …out_clks.uclk_mts = (unsigned int)dml2->v20.dml_core_ctx.states.state_array[lowest_state_idx].dram…  in dml2_validate_and_build_resource()
595 …out_clks.phyclk_khz = (unsigned int)dml2->v20.dml_core_ctx.states.state_array[lowest_state_idx].ph…  in dml2_validate_and_build_resource()
596 …out_clks.socclk_khz = (unsigned int)dml2->v20.dml_core_ctx.states.state_array[lowest_state_idx].so…  in dml2_validate_and_build_resource()
597 …out_clks.ref_dtbclk_khz = (unsigned int)dml2->v20.dml_core_ctx.states.state_array[lowest_state_idx…  in dml2_validate_and_build_resource()
604 	memset(&dml2->v20.scratch, 0, sizeof(struct dml2_wrapper_scratch));  in dml2_validate_and_build_resource()
605 	memset(&dml2->v20.dml_core_ctx.policy, 0, sizeof(struct dml_mode_eval_policy_st));  in dml2_validate_and_build_resource()
606 	memset(&dml2->v20.dml_core_ctx.ms, 0, sizeof(struct mode_support_st));  in dml2_validate_and_build_resource()
607 	memset(&dml2->v20.dml_core_ctx.mp, 0, sizeof(struct mode_program_st));  in dml2_validate_and_build_resource()
642 		out_clks.dispclk_khz = (unsigned int)dml2->v20.dml_core_ctx.mp.Dispclk_calculated * 1000;  in dml2_validate_and_build_resource()
645 			(lowest_state_idx < dml2->v20.dml_core_ctx.states.num_states - 1)) {  in dml2_validate_and_build_resource()
646 			lowest_state_idx = dml2->v20.dml_core_ctx.states.num_states - 1;  in dml2_validate_and_build_resource()
647 …out_clks.dispclk_khz = (unsigned int)dml2->v20.dml_core_ctx.states.state_array[lowest_state_idx].d…  in dml2_validate_and_build_resource()
650 …out_clks.dcfclk_khz = (unsigned int)dml2->v20.dml_core_ctx.states.state_array[lowest_state_idx].dc…  in dml2_validate_and_build_resource()
651 …out_clks.fclk_khz = (unsigned int)dml2->v20.dml_core_ctx.states.state_array[lowest_state_idx].fabr…  in dml2_validate_and_build_resource()
652 …out_clks.uclk_mts = (unsigned int)dml2->v20.dml_core_ctx.states.state_array[lowest_state_idx].dram…  in dml2_validate_and_build_resource()
653 …out_clks.phyclk_khz = (unsigned int)dml2->v20.dml_core_ctx.states.state_array[lowest_state_idx].ph…  in dml2_validate_and_build_resource()
654 …out_clks.socclk_khz = (unsigned int)dml2->v20.dml_core_ctx.states.state_array[lowest_state_idx].so…  in dml2_validate_and_build_resource()
655 …out_clks.ref_dtbclk_khz = (unsigned int)dml2->v20.dml_core_ctx.states.state_array[lowest_state_idx…  in dml2_validate_and_build_resource()
664 		dml2_extract_watermark_set(&context->bw_ctx.bw.dcn.watermarks.a, &dml2->v20.dml_core_ctx);  in dml2_validate_and_build_resource()
665 		dml2_extract_watermark_set(&context->bw_ctx.bw.dcn.watermarks.b, &dml2->v20.dml_core_ctx);  in dml2_validate_and_build_resource()
666 …memcpy(&context->bw_ctx.bw.dcn.watermarks.c, &dml2->v20.g6_temp_read_watermark_set, sizeof(context…  in dml2_validate_and_build_resource()
667 		dml2_extract_watermark_set(&context->bw_ctx.bw.dcn.watermarks.d, &dml2->v20.dml_core_ctx);  in dml2_validate_and_build_resource()
668 		dml2_extract_writeback_wm(context, &dml2->v20.dml_core_ctx);  in dml2_validate_and_build_resource()
670 		context->bw_ctx.dml.vba.StutterPeriod = context->bw_ctx.dml2->v20.dml_core_ctx.mp.StutterPeriod;  in dml2_validate_and_build_resource()
695 	memset(&dml2->v20.scratch, 0, sizeof(struct dml2_wrapper_scratch));  in dml2_validate_only()
696 	memset(&dml2->v20.dml_core_ctx.policy, 0, sizeof(struct dml_mode_eval_policy_st));  in dml2_validate_only()
697 	memset(&dml2->v20.dml_core_ctx.ms, 0, sizeof(struct mode_support_st));  in dml2_validate_only()
698 	memset(&dml2->v20.dml_core_ctx.mp, 0, sizeof(struct mode_program_st));  in dml2_validate_only()
700 	build_unoptimized_policy_settings(dml2->v20.dml_core_ctx.project, &dml2->v20.dml_core_ctx.policy);  in dml2_validate_only()
702 	map_dc_state_into_dml_display_cfg(dml2, context, &dml2->v20.scratch.cur_display_config);  in dml2_validate_only()
704 		 dml2_apply_det_buffer_allocation_policy(dml2, &dml2->v20.scratch.cur_display_config);  in dml2_validate_only()
707 		&dml2->v20.scratch.cur_display_config,  in dml2_validate_only()
708 		&dml2->v20.scratch.mode_support_info);  in dml2_validate_only()
711 …ult = does_configuration_meet_sw_policies(dml2, &dml2->v20.scratch.cur_display_config, &dml2->v20.…  in dml2_validate_only()
767 		(*dml2)->v20.dml_core_ctx.project = dml_project_dcn35;  in dml2_init()
770 		(*dml2)->v20.dml_core_ctx.project = dml_project_dcn351;  in dml2_init()
773 		(*dml2)->v20.dml_core_ctx.project = dml_project_dcn36;  in dml2_init()
776 		(*dml2)->v20.dml_core_ctx.project = dml_project_dcn32;  in dml2_init()
779 		(*dml2)->v20.dml_core_ctx.project = dml_project_dcn321;  in dml2_init()
782 		(*dml2)->v20.dml_core_ctx.project = dml_project_dcn401;  in dml2_init()
785 		(*dml2)->v20.dml_core_ctx.project = dml_project_default;  in dml2_init()
791 	initialize_dml2_ip_params(*dml2, in_dc, &(*dml2)->v20.dml_core_ctx.ip);  in dml2_init()
793 	initialize_dml2_soc_bbox(*dml2, in_dc, &(*dml2)->v20.dml_core_ctx.soc);  in dml2_init()
795 …initialize_dml2_soc_states(*dml2, in_dc, &(*dml2)->v20.dml_core_ctx.soc, &(*dml2)->v20.dml_core_ct…  in dml2_init()
832 	*fclk_change_support = (unsigned int) dml2->v20.dml_core_ctx.ms.support.FCLKChangeSupport[0];  in dml2_extract_dram_and_fclk_change_support()
833 …*dram_clk_change_support = (unsigned int) dml2->v20.dml_core_ctx.ms.support.DRAMClockChangeSupport…  in dml2_extract_dram_and_fclk_change_support()