177 	union dce_dmcu_psr_config_data_reg1 masterCmdData1;  in dce_dmcu_setup_psr()  local
238 	masterCmdData1.u32All = 0;  in dce_dmcu_setup_psr()
239 	masterCmdData1.bits.timehyst_frames = psr_context->timehyst_frames;  in dce_dmcu_setup_psr()
240 	masterCmdData1.bits.hyst_lines = psr_context->hyst_lines;  in dce_dmcu_setup_psr()
241 	masterCmdData1.bits.rfb_update_auto_en =  in dce_dmcu_setup_psr()
243 	masterCmdData1.bits.dp_port_num = psr_context->transmitterId;  in dce_dmcu_setup_psr()
244 	masterCmdData1.bits.dcp_sel = psr_context->controllerId;  in dce_dmcu_setup_psr()
245 	masterCmdData1.bits.phy_type  = psr_context->phyType;  in dce_dmcu_setup_psr()
246 	masterCmdData1.bits.frame_cap_ind =  in dce_dmcu_setup_psr()
248 	masterCmdData1.bits.aux_chan = psr_context->channel;  in dce_dmcu_setup_psr()
249 	masterCmdData1.bits.aux_repeat = psr_context->aux_repeats;  in dce_dmcu_setup_psr()
251 					masterCmdData1.u32All);  in dce_dmcu_setup_psr()
300 	union dce_dmcu_psr_config_data_wait_loop_reg1 masterCmdData1;  in dce_psr_wait_loop()  local
312 	masterCmdData1.u32 = 0;  in dce_psr_wait_loop()
313 	masterCmdData1.bits.wait_loop = wait_loop_number;  in dce_psr_wait_loop()
315 	dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG1), masterCmdData1.u32);  in dce_psr_wait_loop()
608 	union dce_dmcu_psr_config_data_reg1 masterCmdData1;  in dcn10_dmcu_setup_psr()  local
676 	masterCmdData1.u32All = 0;  in dcn10_dmcu_setup_psr()
677 	masterCmdData1.bits.timehyst_frames = psr_context->timehyst_frames;  in dcn10_dmcu_setup_psr()
678 	masterCmdData1.bits.hyst_lines = psr_context->hyst_lines;  in dcn10_dmcu_setup_psr()
679 	masterCmdData1.bits.rfb_update_auto_en =  in dcn10_dmcu_setup_psr()
681 	masterCmdData1.bits.dp_port_num = psr_context->transmitterId;  in dcn10_dmcu_setup_psr()
682 	masterCmdData1.bits.dcp_sel = psr_context->controllerId;  in dcn10_dmcu_setup_psr()
683 	masterCmdData1.bits.phy_type  = psr_context->phyType;  in dcn10_dmcu_setup_psr()
684 	masterCmdData1.bits.frame_cap_ind =  in dcn10_dmcu_setup_psr()
686 	masterCmdData1.bits.aux_chan = psr_context->channel;  in dcn10_dmcu_setup_psr()
687 	masterCmdData1.bits.aux_repeat = psr_context->aux_repeats;  in dcn10_dmcu_setup_psr()
688 	masterCmdData1.bits.allow_smu_optimizations = psr_context->allow_smu_optimizations;  in dcn10_dmcu_setup_psr()
690 					masterCmdData1.u32All);  in dcn10_dmcu_setup_psr()
728 	union dce_dmcu_psr_config_data_wait_loop_reg1 masterCmdData1;  in dcn10_psr_wait_loop()  local
738 	masterCmdData1.u32 = 0;  in dcn10_psr_wait_loop()
739 	masterCmdData1.bits.wait_loop = wait_loop_number;  in dcn10_psr_wait_loop()
741 	dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG1), masterCmdData1.u32);  in dcn10_psr_wait_loop()