Lines Matching refs:WREG32_P
293 WREG32_P(mmUVD_STATUS, 1<<2, ~(1<<2)); in uvd_v4_2_start()
299 WREG32_P(mmSRBM_SOFT_RESET, 0, ~SRBM_SOFT_RESET__SOFT_RESET_UVD_MASK); in uvd_v4_2_start()
306 WREG32_P(mmUVD_MASTINT_EN, 0, ~(1 << 1)); in uvd_v4_2_start()
335 WREG32_P(mmUVD_LMI_CTRL2, 0, ~(1 << 8)); in uvd_v4_2_start()
337 WREG32_P(mmUVD_SOFT_RESET, 0, ~UVD_SOFT_RESET__LMI_SOFT_RESET_MASK); in uvd_v4_2_start()
339 WREG32_P(mmUVD_SOFT_RESET, 0, ~UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK); in uvd_v4_2_start()
341 WREG32_P(mmUVD_SOFT_RESET, 0, ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); in uvd_v4_2_start()
358 WREG32_P(mmUVD_SOFT_RESET, UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK, in uvd_v4_2_start()
361 WREG32_P(mmUVD_SOFT_RESET, 0, ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); in uvd_v4_2_start()
372 WREG32_P(mmUVD_MASTINT_EN, 3<<1, ~(3 << 1)); in uvd_v4_2_start()
374 WREG32_P(mmUVD_STATUS, 0, ~(1<<2)); in uvd_v4_2_start()
398 WREG32_P(mmUVD_RBC_RB_CNTL, rb_bufsz, ~0x11f1f); in uvd_v4_2_start()
440 WREG32_P(mmUVD_LMI_CTRL2, 1 << 8, ~(1 << 8)); in uvd_v4_2_stop()
453 WREG32_P(0x3D49, 0, ~(1 << 2)); in uvd_v4_2_stop()
455 WREG32_P(mmUVD_VCPU_CNTL, 0, ~(1 << 9)); in uvd_v4_2_stop()
687 WREG32_P(mmSRBM_SOFT_RESET, SRBM_SOFT_RESET__SOFT_RESET_UVD_MASK, in uvd_v4_2_soft_reset()