190 static int soc15_query_video_codecs(struct amdgpu_device *adev, bool encode,  in soc15_query_video_codecs()  argument
193 	if (amdgpu_ip_version(adev, VCE_HWIP, 0)) {  in soc15_query_video_codecs()
194 		switch (amdgpu_ip_version(adev, VCE_HWIP, 0)) {  in soc15_query_video_codecs()
206 		switch (amdgpu_ip_version(adev, UVD_HWIP, 0)) {  in soc15_query_video_codecs()
240 static u32 soc15_uvd_ctx_rreg(struct amdgpu_device *adev, u32 reg)  in soc15_uvd_ctx_rreg()  argument
248 	spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags);  in soc15_uvd_ctx_rreg()
251 	spin_unlock_irqrestore(&adev->uvd_ctx_idx_lock, flags);  in soc15_uvd_ctx_rreg()
255 static void soc15_uvd_ctx_wreg(struct amdgpu_device *adev, u32 reg, u32 v)  in soc15_uvd_ctx_wreg()  argument
262 	spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags);  in soc15_uvd_ctx_wreg()
265 	spin_unlock_irqrestore(&adev->uvd_ctx_idx_lock, flags);  in soc15_uvd_ctx_wreg()
268 static u32 soc15_didt_rreg(struct amdgpu_device *adev, u32 reg)  in soc15_didt_rreg()  argument
276 	spin_lock_irqsave(&adev->didt_idx_lock, flags);  in soc15_didt_rreg()
279 	spin_unlock_irqrestore(&adev->didt_idx_lock, flags);  in soc15_didt_rreg()
283 static void soc15_didt_wreg(struct amdgpu_device *adev, u32 reg, u32 v)  in soc15_didt_wreg()  argument
290 	spin_lock_irqsave(&adev->didt_idx_lock, flags);  in soc15_didt_wreg()
293 	spin_unlock_irqrestore(&adev->didt_idx_lock, flags);  in soc15_didt_wreg()
296 static u32 soc15_gc_cac_rreg(struct amdgpu_device *adev, u32 reg)  in soc15_gc_cac_rreg()  argument
301 	spin_lock_irqsave(&adev->gc_cac_idx_lock, flags);  in soc15_gc_cac_rreg()
304 	spin_unlock_irqrestore(&adev->gc_cac_idx_lock, flags);  in soc15_gc_cac_rreg()
308 static void soc15_gc_cac_wreg(struct amdgpu_device *adev, u32 reg, u32 v)  in soc15_gc_cac_wreg()  argument
312 	spin_lock_irqsave(&adev->gc_cac_idx_lock, flags);  in soc15_gc_cac_wreg()
315 	spin_unlock_irqrestore(&adev->gc_cac_idx_lock, flags);  in soc15_gc_cac_wreg()
318 static u32 soc15_se_cac_rreg(struct amdgpu_device *adev, u32 reg)  in soc15_se_cac_rreg()  argument
323 	spin_lock_irqsave(&adev->se_cac_idx_lock, flags);  in soc15_se_cac_rreg()
326 	spin_unlock_irqrestore(&adev->se_cac_idx_lock, flags);  in soc15_se_cac_rreg()
330 static void soc15_se_cac_wreg(struct amdgpu_device *adev, u32 reg, u32 v)  in soc15_se_cac_wreg()  argument
334 	spin_lock_irqsave(&adev->se_cac_idx_lock, flags);  in soc15_se_cac_wreg()
337 	spin_unlock_irqrestore(&adev->se_cac_idx_lock, flags);  in soc15_se_cac_wreg()
340 static u32 soc15_get_config_memsize(struct amdgpu_device *adev)  in soc15_get_config_memsize()  argument
342 	return adev->nbio.funcs->get_memsize(adev);  in soc15_get_config_memsize()
345 static u32 soc15_get_xclk(struct amdgpu_device *adev)  in soc15_get_xclk()  argument
347 	u32 reference_clock = adev->clock.spll.reference_freq;  in soc15_get_xclk()
349 	if (amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(12, 0, 0) ||  in soc15_get_xclk()
350 	    amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(12, 0, 1) ||  in soc15_get_xclk()
351 	    amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 6) ||  in soc15_get_xclk()
352 	    amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 12) ||  in soc15_get_xclk()
353 	    amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 14))  in soc15_get_xclk()
355 	if (amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(10, 0, 0) ||  in soc15_get_xclk()
356 	    amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(10, 0, 1))  in soc15_get_xclk()
363 void soc15_grbm_select(struct amdgpu_device *adev,  in soc15_grbm_select()  argument
375 static bool soc15_read_disabled_bios(struct amdgpu_device *adev)  in soc15_read_disabled_bios()  argument
404 static uint32_t soc15_read_indexed_register(struct amdgpu_device *adev, u32 se_num,  in soc15_read_indexed_register()  argument
409 	mutex_lock(&adev->grbm_idx_mutex);  in soc15_read_indexed_register()
411 		amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff, 0);  in soc15_read_indexed_register()
416 		amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0);  in soc15_read_indexed_register()
417 	mutex_unlock(&adev->grbm_idx_mutex);  in soc15_read_indexed_register()
421 static uint32_t soc15_get_register_value(struct amdgpu_device *adev,  in soc15_get_register_value()  argument
426 		return soc15_read_indexed_register(adev, se_num, sh_num, reg_offset);  in soc15_get_register_value()
429 			return adev->gfx.config.gb_addr_config;  in soc15_get_register_value()
431 			return adev->gfx.config.db_debug2;  in soc15_get_register_value()
436 static int soc15_read_register(struct amdgpu_device *adev, u32 se_num,  in soc15_read_register()  argument
445 		if (!adev->reg_offset[en->hwip][en->inst])  in soc15_read_register()
447 		else if (reg_offset != (adev->reg_offset[en->hwip][en->inst][en->seg]  in soc15_read_register()
451 		*value = soc15_get_register_value(adev,  in soc15_read_register()
471 void soc15_program_register_sequence(struct amdgpu_device *adev,  in soc15_program_register_sequence()  argument
481 		reg =  adev->reg_offset[entry->hwip][entry->instance][entry->segment] + entry->reg;  in soc15_program_register_sequence()
506 static int soc15_asic_baco_reset(struct amdgpu_device *adev)  in soc15_asic_baco_reset()  argument
508 	struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);  in soc15_asic_baco_reset()
512 	if (ras && adev->ras_enabled)  in soc15_asic_baco_reset()
513 		adev->nbio.funcs->enable_doorbell_interrupt(adev, false);  in soc15_asic_baco_reset()
515 	ret = amdgpu_dpm_baco_reset(adev);  in soc15_asic_baco_reset()
520 	if (ras && adev->ras_enabled)  in soc15_asic_baco_reset()
521 		adev->nbio.funcs->enable_doorbell_interrupt(adev, true);  in soc15_asic_baco_reset()
527 soc15_asic_reset_method(struct amdgpu_device *adev)  in soc15_asic_reset_method()  argument
531 	struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);  in soc15_asic_reset_method()
533         if (adev->gmc.xgmi.supported && adev->gmc.xgmi.connected_to_cpu)  in soc15_asic_reset_method()
547 		dev_warn(adev->dev, "Specified reset method:%d isn't supported, using AUTO instead.\n",  in soc15_asic_reset_method()
550 	switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) {  in soc15_asic_reset_method()
558 		if (adev->asic_type == CHIP_VEGA20) {  in soc15_asic_reset_method()
559 			if (adev->psp.sos.fw_version >= 0x80067)  in soc15_asic_reset_method()
560 				baco_reset = amdgpu_dpm_is_baco_supported(adev);  in soc15_asic_reset_method()
565 			if (ras && adev->ras_enabled &&  in soc15_asic_reset_method()
566 			    adev->pm.fw_version <= 0x283400)  in soc15_asic_reset_method()
569 			baco_reset = amdgpu_dpm_is_baco_supported(adev);  in soc15_asic_reset_method()
589 		else if (!(adev->flags & AMD_IS_APU))  in soc15_asic_reset_method()
603 static bool soc15_need_reset_on_resume(struct amdgpu_device *adev)  in soc15_need_reset_on_resume()  argument
609 	if (adev->in_s3 && !pm_resume_via_firmware())  in soc15_need_reset_on_resume()
615 static int soc15_asic_reset(struct amdgpu_device *adev)  in soc15_asic_reset()  argument
623 	if ((adev->apu_flags & AMD_APU_IS_PICASSO ||  in soc15_asic_reset()
624 			!(adev->apu_flags & AMD_APU_IS_RAVEN)) &&  in soc15_asic_reset()
625 			soc15_need_reset_on_resume(adev))  in soc15_asic_reset()
628 	if ((adev->apu_flags & AMD_APU_IS_RAVEN) ||  in soc15_asic_reset()
629 			(adev->apu_flags & AMD_APU_IS_RAVEN2))  in soc15_asic_reset()
633 	switch (soc15_asic_reset_method(adev)) {  in soc15_asic_reset()
635 		dev_info(adev->dev, "PCI reset\n");  in soc15_asic_reset()
636 		return amdgpu_device_pci_reset(adev);  in soc15_asic_reset()
638 		dev_info(adev->dev, "BACO reset\n");  in soc15_asic_reset()
639 		return soc15_asic_baco_reset(adev);  in soc15_asic_reset()
641 		dev_info(adev->dev, "MODE2 reset\n");  in soc15_asic_reset()
642 		return amdgpu_dpm_mode2_reset(adev);  in soc15_asic_reset()
644 		dev_info(adev->dev, "MODE1 reset\n");  in soc15_asic_reset()
645 		return amdgpu_device_mode1_reset(adev);  in soc15_asic_reset()
649 static int soc15_supports_baco(struct amdgpu_device *adev)  in soc15_supports_baco()  argument
651 	switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) {  in soc15_supports_baco()
654 		if (adev->asic_type == CHIP_VEGA20) {  in soc15_supports_baco()
655 			if (adev->psp.sos.fw_version >= 0x80067)  in soc15_supports_baco()
656 				return amdgpu_dpm_is_baco_supported(adev);  in soc15_supports_baco()
659 			return amdgpu_dpm_is_baco_supported(adev);  in soc15_supports_baco()
673 static int soc15_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk)  in soc15_set_uvd_clocks()  argument
686 static int soc15_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32 ecclk)  in soc15_set_vce_clocks()  argument
693 static void soc15_program_aspm(struct amdgpu_device *adev)  in soc15_program_aspm()  argument
695 	if (!amdgpu_device_should_use_aspm(adev))  in soc15_program_aspm()
698 	if (adev->nbio.funcs->program_aspm)  in soc15_program_aspm()
699 		adev->nbio.funcs->program_aspm(adev);  in soc15_program_aspm()
711 static void soc15_reg_base_init(struct amdgpu_device *adev)  in soc15_reg_base_init()  argument
714 	switch (adev->asic_type) {  in soc15_reg_base_init()
719 		vega10_reg_base_init(adev);  in soc15_reg_base_init()
722 		vega20_reg_base_init(adev);  in soc15_reg_base_init()
725 		arct_reg_base_init(adev);  in soc15_reg_base_init()
728 		aldebaran_reg_base_init(adev);  in soc15_reg_base_init()
731 		DRM_ERROR("Unsupported asic type: %d!\n", adev->asic_type);  in soc15_reg_base_init()
736 void soc15_set_virt_ops(struct amdgpu_device *adev)  in soc15_set_virt_ops()  argument
738 	adev->virt.ops = &xgpu_ai_virt_ops;  in soc15_set_virt_ops()
743 	soc15_reg_base_init(adev);  in soc15_set_virt_ops()
746 static bool soc15_need_full_reset(struct amdgpu_device *adev)  in soc15_need_full_reset()  argument
752 static void soc15_get_pcie_usage(struct amdgpu_device *adev, uint64_t *count0,  in soc15_get_pcie_usage()  argument
762 	if (adev->flags & AMD_IS_APU)  in soc15_get_pcie_usage()
799 static void vega20_get_pcie_usage(struct amdgpu_device *adev, uint64_t *count0,  in vega20_get_pcie_usage()  argument
809 	if (adev->flags & AMD_IS_APU)  in vega20_get_pcie_usage()
848 static bool soc15_need_reset_on_init(struct amdgpu_device *adev)  in soc15_need_reset_on_init()  argument
853 	if (adev->asic_type == CHIP_RENOIR)  in soc15_need_reset_on_init()
856 	if (amdgpu_gmc_need_reset_on_init(adev))  in soc15_need_reset_on_init()
858 	if (amdgpu_psp_tos_reload_needed(adev))  in soc15_need_reset_on_init()
863 	if (!amdgpu_passthrough(adev))  in soc15_need_reset_on_init()
866 	if (adev->flags & AMD_IS_APU)  in soc15_need_reset_on_init()
879 static uint64_t soc15_get_pcie_replay_count(struct amdgpu_device *adev)  in soc15_get_pcie_replay_count()  argument
891 static void soc15_pre_asic_init(struct amdgpu_device *adev)  in soc15_pre_asic_init()  argument
893 	gmc_v9_0_restore_registers(adev);  in soc15_pre_asic_init()
962 	struct amdgpu_device *adev = ip_block->adev;  in soc15_common_early_init()  local
964 	adev->nbio.funcs->set_reg_remap(adev);  in soc15_common_early_init()
965 	adev->smc_rreg = NULL;  in soc15_common_early_init()
966 	adev->smc_wreg = NULL;  in soc15_common_early_init()
967 	adev->pcie_rreg = &amdgpu_device_indirect_rreg;  in soc15_common_early_init()
968 	adev->pcie_wreg = &amdgpu_device_indirect_wreg;  in soc15_common_early_init()
969 	adev->pcie_rreg_ext = &amdgpu_device_indirect_rreg_ext;  in soc15_common_early_init()
970 	adev->pcie_wreg_ext = &amdgpu_device_indirect_wreg_ext;  in soc15_common_early_init()
971 	adev->pcie_rreg64 = &amdgpu_device_indirect_rreg64;  in soc15_common_early_init()
972 	adev->pcie_wreg64 = &amdgpu_device_indirect_wreg64;  in soc15_common_early_init()
973 	adev->pcie_rreg64_ext = &amdgpu_device_indirect_rreg64_ext;  in soc15_common_early_init()
974 	adev->pcie_wreg64_ext = &amdgpu_device_indirect_wreg64_ext;  in soc15_common_early_init()
975 	adev->uvd_ctx_rreg = &soc15_uvd_ctx_rreg;  in soc15_common_early_init()
976 	adev->uvd_ctx_wreg = &soc15_uvd_ctx_wreg;  in soc15_common_early_init()
977 	adev->didt_rreg = &soc15_didt_rreg;  in soc15_common_early_init()
978 	adev->didt_wreg = &soc15_didt_wreg;  in soc15_common_early_init()
979 	adev->gc_cac_rreg = &soc15_gc_cac_rreg;  in soc15_common_early_init()
980 	adev->gc_cac_wreg = &soc15_gc_cac_wreg;  in soc15_common_early_init()
981 	adev->se_cac_rreg = &soc15_se_cac_rreg;  in soc15_common_early_init()
982 	adev->se_cac_wreg = &soc15_se_cac_wreg;  in soc15_common_early_init()
984 	adev->rev_id = amdgpu_device_get_rev_id(adev);  in soc15_common_early_init()
985 	adev->external_rev_id = 0xFF;  in soc15_common_early_init()
989 	switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {  in soc15_common_early_init()
991 		adev->asic_funcs = &soc15_asic_funcs;  in soc15_common_early_init()
992 		adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |  in soc15_common_early_init()
1011 		adev->pg_flags = 0;  in soc15_common_early_init()
1012 		adev->external_rev_id = 0x1;  in soc15_common_early_init()
1015 		adev->asic_funcs = &soc15_asic_funcs;  in soc15_common_early_init()
1016 		adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |  in soc15_common_early_init()
1034 		adev->pg_flags = 0;  in soc15_common_early_init()
1035 		adev->external_rev_id = adev->rev_id + 0x14;  in soc15_common_early_init()
1038 		adev->asic_funcs = &vega20_asic_funcs;  in soc15_common_early_init()
1039 		adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |  in soc15_common_early_init()
1057 		adev->pg_flags = 0;  in soc15_common_early_init()
1058 		adev->external_rev_id = adev->rev_id + 0x28;  in soc15_common_early_init()
1062 		adev->asic_funcs = &soc15_asic_funcs;  in soc15_common_early_init()
1064 		if (adev->rev_id >= 0x8)  in soc15_common_early_init()
1065 			adev->apu_flags |= AMD_APU_IS_RAVEN2;  in soc15_common_early_init()
1067 		if (adev->apu_flags & AMD_APU_IS_RAVEN2)  in soc15_common_early_init()
1068 			adev->external_rev_id = adev->rev_id + 0x79;  in soc15_common_early_init()
1069 		else if (adev->apu_flags & AMD_APU_IS_PICASSO)  in soc15_common_early_init()
1070 			adev->external_rev_id = adev->rev_id + 0x41;  in soc15_common_early_init()
1071 		else if (adev->rev_id == 1)  in soc15_common_early_init()
1072 			adev->external_rev_id = adev->rev_id + 0x20;  in soc15_common_early_init()
1074 			adev->external_rev_id = adev->rev_id + 0x01;  in soc15_common_early_init()
1076 		if (adev->apu_flags & AMD_APU_IS_RAVEN2) {  in soc15_common_early_init()
1077 			adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |  in soc15_common_early_init()
1092 			adev->pg_flags = AMD_PG_SUPPORT_SDMA | AMD_PG_SUPPORT_VCN;  in soc15_common_early_init()
1093 		} else if (adev->apu_flags & AMD_APU_IS_PICASSO) {  in soc15_common_early_init()
1094 			adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |  in soc15_common_early_init()
1112 			adev->pg_flags = AMD_PG_SUPPORT_SDMA |  in soc15_common_early_init()
1115 			adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |  in soc15_common_early_init()
1134 			adev->pg_flags = AMD_PG_SUPPORT_SDMA | AMD_PG_SUPPORT_VCN;  in soc15_common_early_init()
1138 		adev->asic_funcs = &vega20_asic_funcs;  in soc15_common_early_init()
1139 		adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |  in soc15_common_early_init()
1153 		adev->pg_flags = AMD_PG_SUPPORT_VCN | AMD_PG_SUPPORT_VCN_DPG;  in soc15_common_early_init()
1154 		adev->external_rev_id = adev->rev_id + 0x32;  in soc15_common_early_init()
1157 		adev->asic_funcs = &soc15_asic_funcs;  in soc15_common_early_init()
1159 		if (adev->apu_flags & AMD_APU_IS_RENOIR)  in soc15_common_early_init()
1160 			adev->external_rev_id = adev->rev_id + 0x91;  in soc15_common_early_init()
1162 			adev->external_rev_id = adev->rev_id + 0xa1;  in soc15_common_early_init()
1163 		adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |  in soc15_common_early_init()
1182 		adev->pg_flags = AMD_PG_SUPPORT_SDMA |  in soc15_common_early_init()
1188 		adev->asic_funcs = &vega20_asic_funcs;  in soc15_common_early_init()
1189 		adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |  in soc15_common_early_init()
1197 		adev->pg_flags = AMD_PG_SUPPORT_VCN_DPG;  in soc15_common_early_init()
1198 		adev->external_rev_id = adev->rev_id + 0x3c;  in soc15_common_early_init()
1203 		adev->asic_funcs = &aqua_vanjaram_asic_funcs;  in soc15_common_early_init()
1204 		adev->cg_flags =  in soc15_common_early_init()
1210 		adev->pg_flags =  in soc15_common_early_init()
1215 		adev->external_rev_id = adev->rev_id + 0x46;  in soc15_common_early_init()
1222 	if (amdgpu_sriov_vf(adev)) {  in soc15_common_early_init()
1223 		amdgpu_virt_init_setting(adev);  in soc15_common_early_init()
1224 		xgpu_ai_mailbox_set_irq_funcs(adev);  in soc15_common_early_init()
1232 	struct amdgpu_device *adev = ip_block->adev;  in soc15_common_late_init()  local
1234 	if (amdgpu_sriov_vf(adev))  in soc15_common_late_init()
1235 		xgpu_ai_mailbox_get_irq(adev);  in soc15_common_late_init()
1240 	adev->nbio.funcs->enable_doorbell_selfring_aperture(adev, true);  in soc15_common_late_init()
1247 	struct amdgpu_device *adev = ip_block->adev;  in soc15_common_sw_init()  local
1249 	if (amdgpu_sriov_vf(adev))  in soc15_common_sw_init()
1250 		xgpu_ai_mailbox_add_irq_id(adev);  in soc15_common_sw_init()
1252 	if (adev->df.funcs &&  in soc15_common_sw_init()
1253 	    adev->df.funcs->sw_init)  in soc15_common_sw_init()
1254 		adev->df.funcs->sw_init(adev);  in soc15_common_sw_init()
1261 	struct amdgpu_device *adev = ip_block->adev;  in soc15_common_sw_fini()  local
1263 	if (adev->df.funcs &&  in soc15_common_sw_fini()
1264 	    adev->df.funcs->sw_fini)  in soc15_common_sw_fini()
1265 		adev->df.funcs->sw_fini(adev);  in soc15_common_sw_fini()
1269 static void soc15_sdma_doorbell_range_init(struct amdgpu_device *adev)  in soc15_sdma_doorbell_range_init()  argument
1274 	if (!amdgpu_sriov_vf(adev)) {  in soc15_sdma_doorbell_range_init()
1275 		for (i = 0; i < adev->sdma.num_instances; i++) {  in soc15_sdma_doorbell_range_init()
1276 			adev->nbio.funcs->sdma_doorbell_range(adev, i,  in soc15_sdma_doorbell_range_init()
1277 				true, adev->doorbell_index.sdma_engine[i] << 1,  in soc15_sdma_doorbell_range_init()
1278 				adev->doorbell_index.sdma_doorbell_range);  in soc15_sdma_doorbell_range_init()
1285 	struct amdgpu_device *adev = ip_block->adev;  in soc15_common_hw_init()  local
1288 	soc15_program_aspm(adev);  in soc15_common_hw_init()
1290 	adev->nbio.funcs->init_registers(adev);  in soc15_common_hw_init()
1295 	if (adev->nbio.funcs->remap_hdp_registers && !amdgpu_sriov_vf(adev))  in soc15_common_hw_init()
1296 		adev->nbio.funcs->remap_hdp_registers(adev);  in soc15_common_hw_init()
1299 	adev->nbio.funcs->enable_doorbell_aperture(adev, true);  in soc15_common_hw_init()
1307 	soc15_sdma_doorbell_range_init(adev);  in soc15_common_hw_init()
1314 	struct amdgpu_device *adev = ip_block->adev;  in soc15_common_hw_fini()  local
1321 	adev->nbio.funcs->enable_doorbell_aperture(adev, false);  in soc15_common_hw_fini()
1322 	adev->nbio.funcs->enable_doorbell_selfring_aperture(adev, false);  in soc15_common_hw_fini()
1324 	if (amdgpu_sriov_vf(adev))  in soc15_common_hw_fini()
1325 		xgpu_ai_mailbox_put_irq(adev);  in soc15_common_hw_fini()
1331 	if ((!amdgpu_sriov_vf(adev)) &&  in soc15_common_hw_fini()
1332 	    (adev->init_lvl->level != AMDGPU_INIT_LEVEL_MINIMAL_XGMI) &&  in soc15_common_hw_fini()
1333 	    adev->nbio.ras_if &&  in soc15_common_hw_fini()
1334 	    amdgpu_ras_is_supported(adev, adev->nbio.ras_if->block)) {  in soc15_common_hw_fini()
1335 		if (adev->nbio.ras &&  in soc15_common_hw_fini()
1336 		    adev->nbio.ras->init_ras_controller_interrupt)  in soc15_common_hw_fini()
1337 			amdgpu_irq_put(adev, &adev->nbio.ras_controller_irq, 0);  in soc15_common_hw_fini()
1338 		if (adev->nbio.ras &&  in soc15_common_hw_fini()
1339 		    adev->nbio.ras->init_ras_err_event_athub_interrupt)  in soc15_common_hw_fini()
1340 			amdgpu_irq_put(adev, &adev->nbio.ras_err_event_athub_irq, 0);  in soc15_common_hw_fini()
1353 	struct amdgpu_device *adev = ip_block->adev;  in soc15_common_resume()  local
1355 	if (soc15_need_reset_on_resume(adev)) {  in soc15_common_resume()
1356 		dev_info(adev->dev, "S3 suspend abort case, let's reset ASIC.\n");  in soc15_common_resume()
1357 		soc15_asic_reset(adev);  in soc15_common_resume()
1367 static void soc15_update_drm_clock_gating(struct amdgpu_device *adev, bool enable)  in soc15_update_drm_clock_gating()  argument
1373 	if (enable && (adev->cg_flags & AMD_CG_SUPPORT_DRM_MGCG))  in soc15_update_drm_clock_gating()
1396 static void soc15_update_drm_light_sleep(struct amdgpu_device *adev, bool enable)  in soc15_update_drm_light_sleep()  argument
1402 	if (enable && (adev->cg_flags & AMD_CG_SUPPORT_DRM_LS))  in soc15_update_drm_light_sleep()
1414 	struct amdgpu_device *adev = ip_block->adev;  in soc15_common_set_clockgating_state()  local
1416 	if (amdgpu_sriov_vf(adev))  in soc15_common_set_clockgating_state()
1419 	switch (amdgpu_ip_version(adev, NBIO_HWIP, 0)) {  in soc15_common_set_clockgating_state()
1423 		adev->nbio.funcs->update_medium_grain_clock_gating(adev,  in soc15_common_set_clockgating_state()
1425 		adev->nbio.funcs->update_medium_grain_light_sleep(adev,  in soc15_common_set_clockgating_state()
1427 		adev->hdp.funcs->update_clock_gating(adev,  in soc15_common_set_clockgating_state()
1429 		soc15_update_drm_clock_gating(adev,  in soc15_common_set_clockgating_state()
1431 		soc15_update_drm_light_sleep(adev,  in soc15_common_set_clockgating_state()
1433 		adev->smuio.funcs->update_rom_clock_gating(adev,  in soc15_common_set_clockgating_state()
1435 		adev->df.funcs->update_medium_grain_clock_gating(adev,  in soc15_common_set_clockgating_state()
1441 		adev->nbio.funcs->update_medium_grain_clock_gating(adev,  in soc15_common_set_clockgating_state()
1443 		adev->nbio.funcs->update_medium_grain_light_sleep(adev,  in soc15_common_set_clockgating_state()
1445 		adev->hdp.funcs->update_clock_gating(adev,  in soc15_common_set_clockgating_state()
1447 		soc15_update_drm_clock_gating(adev,  in soc15_common_set_clockgating_state()
1449 		soc15_update_drm_light_sleep(adev,  in soc15_common_set_clockgating_state()
1454 		adev->hdp.funcs->update_clock_gating(adev,  in soc15_common_set_clockgating_state()
1465 	struct amdgpu_device *adev = ip_block->adev;  in soc15_common_get_clockgating_state()  local
1468 	if (amdgpu_sriov_vf(adev))  in soc15_common_get_clockgating_state()
1471 	if (adev->nbio.funcs && adev->nbio.funcs->get_clockgating_state)  in soc15_common_get_clockgating_state()
1472 		adev->nbio.funcs->get_clockgating_state(adev, flags);  in soc15_common_get_clockgating_state()
1474 	if (adev->hdp.funcs && adev->hdp.funcs->get_clock_gating_state)  in soc15_common_get_clockgating_state()
1475 		adev->hdp.funcs->get_clock_gating_state(adev, flags);  in soc15_common_get_clockgating_state()
1477 	if ((amdgpu_ip_version(adev, MP0_HWIP, 0) != IP_VERSION(13, 0, 2)) &&  in soc15_common_get_clockgating_state()
1478 	    (amdgpu_ip_version(adev, MP0_HWIP, 0) != IP_VERSION(13, 0, 6)) &&  in soc15_common_get_clockgating_state()
1479 	    (amdgpu_ip_version(adev, MP0_HWIP, 0) != IP_VERSION(13, 0, 12)) &&  in soc15_common_get_clockgating_state()
1480 	    (amdgpu_ip_version(adev, MP0_HWIP, 0) != IP_VERSION(13, 0, 14))) {  in soc15_common_get_clockgating_state()
1493 	if (adev->smuio.funcs && adev->smuio.funcs->get_clock_gating_state)  in soc15_common_get_clockgating_state()
1494 		adev->smuio.funcs->get_clock_gating_state(adev, flags);  in soc15_common_get_clockgating_state()
1496 	if (adev->df.funcs && adev->df.funcs->get_clockgating_state)  in soc15_common_get_clockgating_state()
1497 		adev->df.funcs->get_clockgating_state(adev, flags);  in soc15_common_get_clockgating_state()