72 		amdgpu_ring_write(ring, DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0, 0));  in si_dma_ring_emit_ib()
73 	amdgpu_ring_write(ring, DMA_IB_PACKET(DMA_PACKET_INDIRECT_BUFFER, vmid, 0));  in si_dma_ring_emit_ib()
74 	amdgpu_ring_write(ring, (ib->gpu_addr & 0xFFFFFFE0));  in si_dma_ring_emit_ib()
75 	amdgpu_ring_write(ring, (ib->length_dw << 12) | (upper_32_bits(ib->gpu_addr) & 0xFF));  in si_dma_ring_emit_ib()
97 	amdgpu_ring_write(ring, DMA_PACKET(DMA_PACKET_FENCE, 0, 0, 0, 0));  in si_dma_ring_emit_fence()
98 	amdgpu_ring_write(ring, addr & 0xfffffffc);  in si_dma_ring_emit_fence()
99 	amdgpu_ring_write(ring, (upper_32_bits(addr) & 0xff));  in si_dma_ring_emit_fence()
100 	amdgpu_ring_write(ring, seq);  in si_dma_ring_emit_fence()
104 		amdgpu_ring_write(ring, DMA_PACKET(DMA_PACKET_FENCE, 0, 0, 0, 0));  in si_dma_ring_emit_fence()
105 		amdgpu_ring_write(ring, addr & 0xfffffffc);  in si_dma_ring_emit_fence()
106 		amdgpu_ring_write(ring, (upper_32_bits(addr) & 0xff));  in si_dma_ring_emit_fence()
107 		amdgpu_ring_write(ring, upper_32_bits(seq));  in si_dma_ring_emit_fence()
110 	amdgpu_ring_write(ring, DMA_PACKET(DMA_PACKET_TRAP, 0, 0, 0, 0));  in si_dma_ring_emit_fence()
213 	amdgpu_ring_write(ring, DMA_PACKET(DMA_PACKET_WRITE, 0, 0, 0, 1));  in si_dma_ring_test_ring()
214 	amdgpu_ring_write(ring, lower_32_bits(gpu_addr));  in si_dma_ring_test_ring()
215 	amdgpu_ring_write(ring, upper_32_bits(gpu_addr) & 0xff);  in si_dma_ring_test_ring()
216 	amdgpu_ring_write(ring, 0xDEADBEEF);  in si_dma_ring_test_ring()
419 	amdgpu_ring_write(ring, DMA_PACKET(DMA_PACKET_POLL_REG_MEM, 0, 0, 0, 0) |  in si_dma_ring_emit_pipeline_sync()
421 	amdgpu_ring_write(ring, lower_32_bits(addr));  in si_dma_ring_emit_pipeline_sync()
422 	amdgpu_ring_write(ring, (0xff << 16) | upper_32_bits(addr)); /* retry, addr_hi */  in si_dma_ring_emit_pipeline_sync()
423 	amdgpu_ring_write(ring, 0xffffffff); /* mask */  in si_dma_ring_emit_pipeline_sync()
424 	amdgpu_ring_write(ring, seq); /* value */  in si_dma_ring_emit_pipeline_sync()
425 	amdgpu_ring_write(ring, (3 << 28) | 0x20); /* func(equal) | poll interval */  in si_dma_ring_emit_pipeline_sync()
444 	amdgpu_ring_write(ring, DMA_PACKET(DMA_PACKET_POLL_REG_MEM, 0, 0, 0, 0));  in si_dma_ring_emit_vm_flush()
445 	amdgpu_ring_write(ring, VM_INVALIDATE_REQUEST);  in si_dma_ring_emit_vm_flush()
446 	amdgpu_ring_write(ring, 0xff << 16); /* retry */  in si_dma_ring_emit_vm_flush()
447 	amdgpu_ring_write(ring, 1 << vmid); /* mask */  in si_dma_ring_emit_vm_flush()
448 	amdgpu_ring_write(ring, 0); /* value */  in si_dma_ring_emit_vm_flush()
449 	amdgpu_ring_write(ring, (0 << 28) | 0x20); /* func(always) | poll interval */  in si_dma_ring_emit_vm_flush()
455 	amdgpu_ring_write(ring, DMA_PACKET(DMA_PACKET_SRBM_WRITE, 0, 0, 0, 0));  in si_dma_ring_emit_wreg()
456 	amdgpu_ring_write(ring, (0xf << 16) | reg);  in si_dma_ring_emit_wreg()
457 	amdgpu_ring_write(ring, val);  in si_dma_ring_emit_wreg()