272 	struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring);  in sdma_v7_0_ring_insert_nop()  local
276 		if (sdma && sdma->burst_nop && (i == 0))  in sdma_v7_0_ring_insert_nop()
430 	for (i = 0; i < adev->sdma.num_instances; i++) {  in sdma_v7_0_gfx_stop()
485 	for (i = 0; i < adev->sdma.num_instances; i++) {  in sdma_v7_0_enable()
513 	ring = &adev->sdma.instance[i].ring;  in sdma_v7_0_gfx_resume_instance()
590 					      adev->doorbell_index.sdma_doorbell_range * adev->sdma.num_instances);  in sdma_v7_0_gfx_resume_instance()
664 	for (i = 0; i < adev->sdma.num_instances; i++) {  in sdma_v7_0_gfx_resume()
691 	for (i = 0; i < adev->sdma.num_instances; i++) {  in sdma_v12_0_free_ucode_buffer()
692 		amdgpu_bo_free_kernel(&adev->sdma.instance[i].sdma_fw_obj,  in sdma_v12_0_free_ucode_buffer()
693 				      &adev->sdma.instance[i].sdma_fw_gpu_addr,  in sdma_v12_0_free_ucode_buffer()
694 				      (void **)&adev->sdma.instance[i].sdma_fw_ptr);  in sdma_v12_0_free_ucode_buffer()
717 	if (!adev->sdma.instance[0].fw)  in sdma_v7_0_load_microcode()
721 		adev->sdma.instance[0].fw->data;  in sdma_v7_0_load_microcode()
724 	fw_data = (const __le32 *)(adev->sdma.instance[0].fw->data +  in sdma_v7_0_load_microcode()
728 	for (i = 0; i < adev->sdma.num_instances; i++) {  in sdma_v7_0_load_microcode()
732 					      &adev->sdma.instance[i].sdma_fw_obj,  in sdma_v7_0_load_microcode()
733 					      &adev->sdma.instance[i].sdma_fw_gpu_addr,  in sdma_v7_0_load_microcode()
734 					      (void **)&adev->sdma.instance[i].sdma_fw_ptr);  in sdma_v7_0_load_microcode()
740 		memcpy(adev->sdma.instance[i].sdma_fw_ptr, fw_data, fw_size);  in sdma_v7_0_load_microcode()
742 		amdgpu_bo_kunmap(adev->sdma.instance[i].sdma_fw_obj);  in sdma_v7_0_load_microcode()
743 		amdgpu_bo_unreserve(adev->sdma.instance[i].sdma_fw_obj);  in sdma_v7_0_load_microcode()
750 			lower_32_bits(adev->sdma.instance[i].sdma_fw_gpu_addr));  in sdma_v7_0_load_microcode()
752 			upper_32_bits(adev->sdma.instance[i].sdma_fw_gpu_addr));  in sdma_v7_0_load_microcode()
787 	for (i = 0; i < adev->sdma.num_instances; i++) {  in sdma_v7_0_soft_reset()
822 	for (i = 0; i < adev->sdma.num_instances; i++) {  in sdma_v7_0_check_soft_reset()
823 		ring = &adev->sdma.instance[i].ring;  in sdma_v7_0_check_soft_reset()
840 	for (i = 0; i < adev->sdma.num_instances; i++) {  in sdma_v7_0_reset_queue()
841 		if (ring == &adev->sdma.instance[i].ring)  in sdma_v7_0_reset_queue()
845 	if (i == adev->sdma.num_instances) {  in sdma_v7_0_reset_queue()
1219 	struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring);  in sdma_v7_0_ring_pad_ib()  local
1225 		if (sdma && sdma->burst_nop && (i == 0))  in sdma_v7_0_ring_pad_ib()
1341 			      &adev->sdma.trap_irq);  in sdma_v7_0_sw_init()
1345 	for (i = 0; i < adev->sdma.num_instances; i++) {  in sdma_v7_0_sw_init()
1346 		ring = &adev->sdma.instance[i].ring;  in sdma_v7_0_sw_init()
1360 				     &adev->sdma.trap_irq,  in sdma_v7_0_sw_init()
1367 	adev->sdma.supported_reset =  in sdma_v7_0_sw_init()
1368 		amdgpu_get_soft_full_reset_mask(&adev->sdma.instance[0].ring);  in sdma_v7_0_sw_init()
1369 	adev->sdma.supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE;  in sdma_v7_0_sw_init()
1375 	ptr = kcalloc(adev->sdma.num_instances * reg_count, sizeof(uint32_t), GFP_KERNEL);  in sdma_v7_0_sw_init()
1377 		adev->sdma.ip_dump = ptr;  in sdma_v7_0_sw_init()
1389 	for (i = 0; i < adev->sdma.num_instances; i++)  in sdma_v7_0_sw_fini()
1390 		amdgpu_ring_fini(&adev->sdma.instance[i].ring);  in sdma_v7_0_sw_fini()
1398 	kfree(adev->sdma.ip_dump);  in sdma_v7_0_sw_fini()
1438 	for (i = 0; i < adev->sdma.num_instances; i++) {  in sdma_v7_0_is_idle()
1566 			amdgpu_fence_process(&adev->sdma.instance[instances].ring);  in sdma_v7_0_process_trap_irq()
1606 	if (!adev->sdma.ip_dump)  in sdma_v7_0_print_ip_state()
1609 	drm_printf(p, "num_instances:%d\n", adev->sdma.num_instances);  in sdma_v7_0_print_ip_state()
1610 	for (i = 0; i < adev->sdma.num_instances; i++) {  in sdma_v7_0_print_ip_state()
1616 				   adev->sdma.ip_dump[instance_offset + j]);  in sdma_v7_0_print_ip_state()
1627 	if (!adev->sdma.ip_dump)  in sdma_v7_0_dump_ip_state()
1631 	for (i = 0; i < adev->sdma.num_instances; i++) {  in sdma_v7_0_dump_ip_state()
1634 			adev->sdma.ip_dump[instance_offset + j] =  in sdma_v7_0_dump_ip_state()
1702 	for (i = 0; i < adev->sdma.num_instances; i++) {  in sdma_v7_0_set_ring_funcs()
1703 		adev->sdma.instance[i].ring.funcs = &sdma_v7_0_ring_funcs;  in sdma_v7_0_set_ring_funcs()
1704 		adev->sdma.instance[i].ring.me = i;  in sdma_v7_0_set_ring_funcs()
1719 	adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_INSTANCE0 +  in sdma_v7_0_set_irq_funcs()
1720 					adev->sdma.num_instances;  in sdma_v7_0_set_irq_funcs()
1721 	adev->sdma.trap_irq.funcs = &sdma_v7_0_trap_irq_funcs;  in sdma_v7_0_set_irq_funcs()
1722 	adev->sdma.illegal_inst_irq.funcs = &sdma_v7_0_illegal_inst_irq_funcs;  in sdma_v7_0_set_irq_funcs()
1807 	adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring;  in sdma_v7_0_set_buffer_funcs()
1822 	for (i = 0; i < adev->sdma.num_instances; i++) {  in sdma_v7_0_set_vm_pte_funcs()
1824 			&adev->sdma.instance[i].ring.sched;  in sdma_v7_0_set_vm_pte_funcs()
1826 	adev->vm_manager.vm_pte_num_scheds = adev->sdma.num_instances;  in sdma_v7_0_set_vm_pte_funcs()