241 	struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring);  in sdma_v6_0_ring_insert_nop()  local
245 		if (sdma && sdma->burst_nop && (i == 0))  in sdma_v6_0_ring_insert_nop()
399 	for (i = 0; i < adev->sdma.num_instances; i++) {  in sdma_v6_0_gfx_stop()
435 		for (i = 0; i < adev->sdma.num_instances; i++) {  in sdma_v6_0_ctxempty_int_enable()
465 	for (i = 0; i < adev->sdma.num_instances; i++) {  in sdma_v6_0_enable()
492 	ring = &adev->sdma.instance[i].ring;  in sdma_v6_0_gfx_resume_instance()
567 					      adev->doorbell_index.sdma_doorbell_range * adev->sdma.num_instances);  in sdma_v6_0_gfx_resume_instance()
635 	for (i = 0; i < adev->sdma.num_instances; i++) {  in sdma_v6_0_gfx_resume()
676 	if (!adev->sdma.instance[0].fw)  in sdma_v6_0_load_microcode()
685 		hdr = (const struct sdma_firmware_header_v2_0 *)adev->sdma.instance[0].fw->data;  in sdma_v6_0_load_microcode()
690 			(adev->sdma.instance[0].fw->data +  in sdma_v6_0_load_microcode()
705 			(adev->sdma.instance[0].fw->data +  in sdma_v6_0_load_microcode()
717 		for (i = 0; i < adev->sdma.num_instances; i++) {  in sdma_v6_0_load_microcode()
719 			hdr = (const struct sdma_firmware_header_v2_0 *)adev->sdma.instance[0].fw->data;  in sdma_v6_0_load_microcode()
724 				(adev->sdma.instance[0].fw->data +  in sdma_v6_0_load_microcode()
735 …	WREG32(sdma_v6_0_get_reg_offset(adev, i, regSDMA0_UCODE_ADDR), adev->sdma.instance[0].fw_version);  in sdma_v6_0_load_microcode()
741 				(adev->sdma.instance[0].fw->data +  in sdma_v6_0_load_microcode()
752 …	WREG32(sdma_v6_0_get_reg_offset(adev, i, regSDMA0_UCODE_ADDR), adev->sdma.instance[0].fw_version);  in sdma_v6_0_load_microcode()
767 	for (i = 0; i < adev->sdma.num_instances; i++) {  in sdma_v6_0_soft_reset()
802 	for (i = 0; i < adev->sdma.num_instances; i++) {  in sdma_v6_0_check_soft_reset()
803 		ring = &adev->sdma.instance[i].ring;  in sdma_v6_0_check_soft_reset()
1171 	struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring);  in sdma_v6_0_ring_pad_ib()  local
1177 		if (sdma && sdma->burst_nop && (i == 0))  in sdma_v6_0_ring_pad_ib()
1291 		adev->sdma.ras = &sdma_v6_0_3_ras;  in sdma_v6_0_set_ras_funcs()
1328 			      &adev->sdma.trap_irq);  in sdma_v6_0_sw_init()
1332 	for (i = 0; i < adev->sdma.num_instances; i++) {  in sdma_v6_0_sw_init()
1333 		ring = &adev->sdma.instance[i].ring;  in sdma_v6_0_sw_init()
1347 				     &adev->sdma.trap_irq,  in sdma_v6_0_sw_init()
1354 	adev->sdma.supported_reset =  in sdma_v6_0_sw_init()
1355 		amdgpu_get_soft_full_reset_mask(&adev->sdma.instance[0].ring);  in sdma_v6_0_sw_init()
1360 		if (adev->sdma.instance[0].fw_version >= 21)  in sdma_v6_0_sw_init()
1361 			adev->sdma.supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE;  in sdma_v6_0_sw_init()
1373 	ptr = kcalloc(adev->sdma.num_instances * reg_count, sizeof(uint32_t), GFP_KERNEL);  in sdma_v6_0_sw_init()
1375 		adev->sdma.ip_dump = ptr;  in sdma_v6_0_sw_init()
1391 	for (i = 0; i < adev->sdma.num_instances; i++)  in sdma_v6_0_sw_fini()
1392 		amdgpu_ring_fini(&adev->sdma.instance[i].ring);  in sdma_v6_0_sw_fini()
1397 	kfree(adev->sdma.ip_dump);  in sdma_v6_0_sw_fini()
1437 	for (i = 0; i < adev->sdma.num_instances; i++) {  in sdma_v6_0_is_idle()
1517 	for (i = 0; i < adev->sdma.num_instances; i++) {  in sdma_v6_0_reset_queue()
1518 		if (ring == &adev->sdma.instance[i].ring)  in sdma_v6_0_reset_queue()
1522 	if (i == adev->sdma.num_instances) {  in sdma_v6_0_reset_queue()
1588 			amdgpu_fence_process(&adev->sdma.instance[instances].ring);  in sdma_v6_0_process_trap_irq()
1628 	if (!adev->sdma.ip_dump)  in sdma_v6_0_print_ip_state()
1631 	drm_printf(p, "num_instances:%d\n", adev->sdma.num_instances);  in sdma_v6_0_print_ip_state()
1632 	for (i = 0; i < adev->sdma.num_instances; i++) {  in sdma_v6_0_print_ip_state()
1638 				   adev->sdma.ip_dump[instance_offset + j]);  in sdma_v6_0_print_ip_state()
1649 	if (!adev->sdma.ip_dump)  in sdma_v6_0_dump_ip_state()
1653 	for (i = 0; i < adev->sdma.num_instances; i++) {  in sdma_v6_0_dump_ip_state()
1656 			adev->sdma.ip_dump[instance_offset + j] =  in sdma_v6_0_dump_ip_state()
1723 	for (i = 0; i < adev->sdma.num_instances; i++) {  in sdma_v6_0_set_ring_funcs()
1724 		adev->sdma.instance[i].ring.funcs = &sdma_v6_0_ring_funcs;  in sdma_v6_0_set_ring_funcs()
1725 		adev->sdma.instance[i].ring.me = i;  in sdma_v6_0_set_ring_funcs()
1740 	adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_INSTANCE0 +  in sdma_v6_0_set_irq_funcs()
1741 					adev->sdma.num_instances;  in sdma_v6_0_set_irq_funcs()
1742 	adev->sdma.trap_irq.funcs = &sdma_v6_0_trap_irq_funcs;  in sdma_v6_0_set_irq_funcs()
1743 	adev->sdma.illegal_inst_irq.funcs = &sdma_v6_0_illegal_inst_irq_funcs;  in sdma_v6_0_set_irq_funcs()
1811 	adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring;  in sdma_v6_0_set_buffer_funcs()
1826 	for (i = 0; i < adev->sdma.num_instances; i++) {  in sdma_v6_0_set_vm_pte_funcs()
1828 			&adev->sdma.instance[i].ring.sched;  in sdma_v6_0_set_vm_pte_funcs()
1830 	adev->vm_manager.vm_pte_num_scheds = adev->sdma.num_instances;  in sdma_v6_0_set_vm_pte_funcs()