Lines Matching refs:gmc
763 adev->gmc.vm_fault.num_types = 1; in gmc_v9_0_set_irq_funcs()
764 adev->gmc.vm_fault.funcs = &gmc_v9_0_irq_funcs; in gmc_v9_0_set_irq_funcs()
767 !adev->gmc.xgmi.connected_to_cpu && in gmc_v9_0_set_irq_funcs()
768 !adev->gmc.is_app_apu) { in gmc_v9_0_set_irq_funcs()
769 adev->gmc.ecc_irq.num_types = 1; in gmc_v9_0_set_irq_funcs()
770 adev->gmc.ecc_irq.funcs = &gmc_v9_0_ecc_funcs; in gmc_v9_0_set_irq_funcs()
878 spin_lock(&adev->gmc.invalidate_lock); in gmc_v9_0_flush_gpu_tlb()
940 spin_unlock(&adev->gmc.invalidate_lock); in gmc_v9_0_flush_gpu_tlb()
1114 if (!adev->gmc.translate_further) in gmc_v9_0_get_vm_pde()
1168 adev->gmc.xgmi.connected_to_cpu) in gmc_v9_0_get_coherence_flags()
1310 if (adev->gmc.is_app_apu && vm->mem_id >= 0) { in gmc_v9_0_override_vm_pte_flags()
1311 local_node = adev->gmc.mem_partitions[vm->mem_id].numa.node; in gmc_v9_0_override_vm_pte_flags()
1406 switch (adev->gmc.num_mem_partitions) { in gmc_v9_0_query_vf_memory_partition()
1435 adev->gmc.reset_flags |= AMDGPU_GMC_INIT_RESET_NPS; in gmc_v9_0_need_reset_on_init()
1459 adev->gmc.gmc_funcs = &gmc_v9_0_gmc_funcs; in gmc_v9_0_set_gmc_funcs()
1493 if (!adev->gmc.xgmi.connected_to_cpu) in gmc_v9_0_set_umc_funcs()
1509 if (!adev->gmc.xgmi.connected_to_cpu && !adev->gmc.is_app_apu) in gmc_v9_0_set_umc_funcs()
1578 if (!adev->gmc.xgmi.connected_to_cpu) { in gmc_v9_0_set_mca_ras_funcs()
1591 if (!adev->gmc.xgmi.connected_to_cpu) in gmc_v9_0_set_xgmi_ras_funcs()
1592 adev->gmc.xgmi.ras = &xgmi_ras; in gmc_v9_0_set_xgmi_ras_funcs()
1601 adev->gmc.supported_nps_modes = 0; in gmc_v9_0_init_nps_details()
1612 adev->gmc.supported_nps_modes |= BIT(i); in gmc_v9_0_init_nps_details()
1622 adev->gmc.supported_nps_modes = in gmc_v9_0_init_nps_details()
1643 adev->gmc.xgmi.supported = true; in gmc_v9_0_early_init()
1646 adev->gmc.xgmi.supported = true; in gmc_v9_0_early_init()
1647 adev->gmc.xgmi.connected_to_cpu = in gmc_v9_0_early_init()
1661 adev->gmc.is_app_apu = (pkg_type == AMDGPU_PKG_TYPE_APU && in gmc_v9_0_early_init()
1675 adev->gmc.shared_aperture_start = 0x2000000000000000ULL; in gmc_v9_0_early_init()
1676 adev->gmc.shared_aperture_end = in gmc_v9_0_early_init()
1677 adev->gmc.shared_aperture_start + (4ULL << 30) - 1; in gmc_v9_0_early_init()
1678 adev->gmc.private_aperture_start = 0x1000000000000000ULL; in gmc_v9_0_early_init()
1679 adev->gmc.private_aperture_end = in gmc_v9_0_early_init()
1680 adev->gmc.private_aperture_start + (4ULL << 30) - 1; in gmc_v9_0_early_init()
1681 adev->gmc.noretry_flags = AMDGPU_VM_NORETRY_FLAGS_TF; in gmc_v9_0_early_init()
1717 return amdgpu_irq_get(adev, &adev->gmc.vm_fault, 0); in gmc_v9_0_late_init()
1728 base += adev->gmc.xgmi.physical_node_id * adev->gmc.xgmi.node_segment_size; in gmc_v9_0_vram_gtt_location()
1729 if (adev->gmc.xgmi.connected_to_cpu) { in gmc_v9_0_vram_gtt_location()
1742 adev->gmc.xgmi.physical_node_id * adev->gmc.xgmi.node_segment_size; in gmc_v9_0_vram_gtt_location()
1759 if (!adev->gmc.is_app_apu) { in gmc_v9_0_mc_init()
1760 adev->gmc.mc_vram_size = in gmc_v9_0_mc_init()
1764 adev->gmc.mc_vram_size = 0; in gmc_v9_0_mc_init()
1766 adev->gmc.real_vram_size = adev->gmc.mc_vram_size; in gmc_v9_0_mc_init()
1769 !adev->gmc.xgmi.connected_to_cpu) { in gmc_v9_0_mc_init()
1774 adev->gmc.aper_base = pci_resource_start(adev->pdev, 0); in gmc_v9_0_mc_init()
1775 adev->gmc.aper_size = pci_resource_len(adev->pdev, 0); in gmc_v9_0_mc_init()
1792 (adev->gmc.xgmi.supported && in gmc_v9_0_mc_init()
1793 adev->gmc.xgmi.connected_to_cpu)) { in gmc_v9_0_mc_init()
1794 adev->gmc.aper_base = in gmc_v9_0_mc_init()
1796 adev->gmc.xgmi.physical_node_id * in gmc_v9_0_mc_init()
1797 adev->gmc.xgmi.node_segment_size; in gmc_v9_0_mc_init()
1798 adev->gmc.aper_size = adev->gmc.real_vram_size; in gmc_v9_0_mc_init()
1802 adev->gmc.visible_vram_size = adev->gmc.aper_size; in gmc_v9_0_mc_init()
1816 adev->gmc.gart_size = 512ULL << 20; in gmc_v9_0_mc_init()
1821 adev->gmc.gart_size = 1024ULL << 20; in gmc_v9_0_mc_init()
1825 adev->gmc.gart_size = (u64)amdgpu_gart_size << 20; in gmc_v9_0_mc_init()
1828 adev->gmc.gart_size += adev->pm.smu_prv_buffer_size; in gmc_v9_0_mc_init()
1830 gmc_v9_0_vram_gtt_location(adev, &adev->gmc); in gmc_v9_0_mc_init()
1844 if (adev->gmc.xgmi.connected_to_cpu) { in gmc_v9_0_gart_init()
1845 adev->gmc.vmid0_page_table_depth = 1; in gmc_v9_0_gart_init()
1846 adev->gmc.vmid0_page_table_block_size = 12; in gmc_v9_0_gart_init()
1848 adev->gmc.vmid0_page_table_depth = 0; in gmc_v9_0_gart_init()
1849 adev->gmc.vmid0_page_table_block_size = 0; in gmc_v9_0_gart_init()
1860 if (!adev->gmc.real_vram_size) { in gmc_v9_0_gart_init()
1870 if (adev->gmc.xgmi.connected_to_cpu) in gmc_v9_0_gart_init()
1889 adev->gmc.sdpif_register = RREG32_SOC15(DCE, 0, mmDCHUBBUB_SDPIF_MMIO_CNTRL_0); in gmc_v9_0_save_registers()
1908 valid = (adev->gmc.num_mem_partitions == 1); in gmc_v9_0_validate_partition_info()
1911 valid = (adev->gmc.num_mem_partitions == 2); in gmc_v9_0_validate_partition_info()
1914 valid = (adev->gmc.num_mem_partitions == 3 || in gmc_v9_0_validate_partition_info()
1915 adev->gmc.num_mem_partitions == 4); in gmc_v9_0_validate_partition_info()
1971 adev->gmc.num_mem_partitions = num_ranges; in gmc_v9_0_init_acpi_mem_ranges()
1986 adev->gmc.num_mem_partitions = 0; in gmc_v9_0_init_sw_mem_ranges()
1989 adev->gmc.num_mem_partitions = 1; in gmc_v9_0_init_sw_mem_ranges()
1992 adev->gmc.num_mem_partitions = 2; in gmc_v9_0_init_sw_mem_ranges()
1996 adev->gmc.num_mem_partitions = 3; in gmc_v9_0_init_sw_mem_ranges()
1998 adev->gmc.num_mem_partitions = 4; in gmc_v9_0_init_sw_mem_ranges()
2001 adev->gmc.num_mem_partitions = 1; in gmc_v9_0_init_sw_mem_ranges()
2007 &adev->gmc.num_mem_partitions); in gmc_v9_0_init_sw_mem_ranges()
2010 for (i = 1; i < adev->gmc.num_mem_partitions; ++i) { in gmc_v9_0_init_sw_mem_ranges()
2017 if (!adev->gmc.num_mem_partitions) { in gmc_v9_0_init_sw_mem_ranges()
2020 adev->gmc.num_mem_partitions = 1; in gmc_v9_0_init_sw_mem_ranges()
2023 size = (adev->gmc.real_vram_size + SZ_16M) >> AMDGPU_GPU_PAGE_SHIFT; in gmc_v9_0_init_sw_mem_ranges()
2024 size /= adev->gmc.num_mem_partitions; in gmc_v9_0_init_sw_mem_ranges()
2026 for (i = 0; i < adev->gmc.num_mem_partitions; ++i) { in gmc_v9_0_init_sw_mem_ranges()
2034 l = adev->gmc.num_mem_partitions - 1; in gmc_v9_0_init_sw_mem_ranges()
2039 (adev->gmc.real_vram_size >> AMDGPU_GPU_PAGE_SHIFT) - 1; in gmc_v9_0_init_sw_mem_ranges()
2041 adev->gmc.real_vram_size - in gmc_v9_0_init_sw_mem_ranges()
2049 adev->gmc.mem_partitions = kcalloc(MAX_MEM_RANGES, in gmc_v9_0_init_mem_ranges()
2052 if (!adev->gmc.mem_partitions) in gmc_v9_0_init_mem_ranges()
2056 if (adev->gmc.is_app_apu) in gmc_v9_0_init_mem_ranges()
2057 gmc_v9_0_init_acpi_mem_ranges(adev, adev->gmc.mem_partitions); in gmc_v9_0_init_mem_ranges()
2059 gmc_v9_0_init_sw_mem_ranges(adev, adev->gmc.mem_partitions); in gmc_v9_0_init_mem_ranges()
2076 adev->gmc.vram_type = AMDGPU_VRAM_TYPE_HBM; in gmc_v9_4_3_init_vram_info()
2077 adev->gmc.vram_width = 128 * 64; in gmc_v9_4_3_init_vram_info()
2090 spin_lock_init(&adev->gmc.invalidate_lock); in gmc_v9_0_sw_init()
2096 adev->gmc.vram_type = AMDGPU_VRAM_TYPE_DDR4; in gmc_v9_0_sw_init()
2097 adev->gmc.vram_width = 64 * 64; in gmc_v9_0_sw_init()
2099 adev->gmc.vram_type = AMDGPU_VRAM_TYPE_HBM; in gmc_v9_0_sw_init()
2100 adev->gmc.vram_width = 128 * 64; in gmc_v9_0_sw_init()
2110 adev->gmc.vram_width = 2048; in gmc_v9_0_sw_init()
2112 adev->gmc.vram_width = vram_width; in gmc_v9_0_sw_init()
2114 if (!adev->gmc.vram_width) { in gmc_v9_0_sw_init()
2125 adev->gmc.vram_width = numchan * chansize; in gmc_v9_0_sw_init()
2129 adev->gmc.vram_type = vram_type; in gmc_v9_0_sw_init()
2130 adev->gmc.vram_vendor = vram_vendor; in gmc_v9_0_sw_init()
2143 adev->gmc.translate_further = in gmc_v9_0_sw_init()
2163 adev->gmc.translate_further = adev->vm_manager.num_level > 1; in gmc_v9_0_sw_init()
2172 adev->gmc.translate_further = adev->vm_manager.num_level > 1; in gmc_v9_0_sw_init()
2184 adev->gmc.translate_further = adev->vm_manager.num_level > 1; in gmc_v9_0_sw_init()
2192 &adev->gmc.vm_fault); in gmc_v9_0_sw_init()
2198 &adev->gmc.vm_fault); in gmc_v9_0_sw_init()
2204 &adev->gmc.vm_fault); in gmc_v9_0_sw_init()
2210 !adev->gmc.xgmi.connected_to_cpu && in gmc_v9_0_sw_init()
2211 !adev->gmc.is_app_apu) { in gmc_v9_0_sw_init()
2214 &adev->gmc.ecc_irq); in gmc_v9_0_sw_init()
2223 adev->gmc.mc_mask = 0xffffffffffffULL; /* 48 bit MC */ in gmc_v9_0_sw_init()
2299 if (!adev->gmc.real_vram_size) { in gmc_v9_0_sw_fini()
2305 amdgpu_bo_free_kernel(&adev->gmc.pdb0_bo, NULL, &adev->gmc.ptr_pdb0); in gmc_v9_0_sw_fini()
2308 adev->gmc.num_mem_partitions = 0; in gmc_v9_0_sw_fini()
2309 kfree(adev->gmc.mem_partitions); in gmc_v9_0_sw_fini()
2352 WREG32_SOC15(DCE, 0, mmDCHUBBUB_SDPIF_MMIO_CNTRL_0, adev->gmc.sdpif_register); in gmc_v9_0_restore_registers()
2353 WARN_ON(adev->gmc.sdpif_register != in gmc_v9_0_restore_registers()
2367 if (adev->gmc.xgmi.connected_to_cpu) in gmc_v9_0_gart_enable()
2388 (unsigned int)(adev->gmc.gart_size >> 20)); in gmc_v9_0_gart_enable()
2389 if (adev->gmc.pdb0_bo) in gmc_v9_0_gart_enable()
2391 (unsigned long long)amdgpu_bo_gpu_offset(adev->gmc.pdb0_bo)); in gmc_v9_0_gart_enable()
2404 adev->gmc.flush_pasid_uses_kiq = true; in gmc_v9_0_hw_init()
2411 adev->gmc.flush_tlb_needs_extra_type_2 = in gmc_v9_0_hw_init()
2413 adev->gmc.xgmi.num_physical_nodes; in gmc_v9_0_hw_init()
2418 adev->gmc.flush_tlb_needs_extra_type_0 = in gmc_v9_0_hw_init()
2508 amdgpu_irq_put(adev, &adev->gmc.vm_fault, 0); in gmc_v9_0_hw_fini()
2510 if (adev->gmc.ecc_irq.funcs && in gmc_v9_0_hw_fini()
2512 amdgpu_irq_put(adev, &adev->gmc.ecc_irq, 0); in gmc_v9_0_hw_fini()
2531 if (adev->gmc.reset_flags & AMDGPU_GMC_INIT_RESET_NPS) { in gmc_v9_0_resume()
2532 gmc_v9_0_init_sw_mem_ranges(adev, adev->gmc.mem_partitions); in gmc_v9_0_resume()
2533 adev->gmc.reset_flags &= ~AMDGPU_GMC_INIT_RESET_NPS; in gmc_v9_0_resume()