188 	struct amdgpu_crtc *amdgpu_crtc = adev->mode_info.crtcs[crtc_id];  in dce_v8_0_page_flip()  local
189 	struct drm_framebuffer *fb = amdgpu_crtc->base.primary->fb;  in dce_v8_0_page_flip()
192 	WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, async ?  in dce_v8_0_page_flip()
195 	WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset,  in dce_v8_0_page_flip()
198 	WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,  in dce_v8_0_page_flip()
201 	WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,  in dce_v8_0_page_flip()
204 	RREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset);  in dce_v8_0_page_flip()
467 	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);  in dce_v8_0_program_fmt()  local
532 	WREG32(mmFMT_BIT_DEPTH_CONTROL + amdgpu_crtc->crtc_offset, tmp);  in dce_v8_0_program_fmt()
550 				       struct amdgpu_crtc *amdgpu_crtc,  in dce_v8_0_line_buffer_adjust()  argument
554 	u32 pipe_offset = amdgpu_crtc->crtc_id * 0x8;  in dce_v8_0_line_buffer_adjust()
563 	if (amdgpu_crtc->base.enabled && mode) {  in dce_v8_0_line_buffer_adjust()
583 	WREG32(mmLB_MEMORY_CTRL + amdgpu_crtc->crtc_offset,  in dce_v8_0_line_buffer_adjust()
596 	if (amdgpu_crtc->base.enabled && mode) {  in dce_v8_0_line_buffer_adjust()
980 					struct amdgpu_crtc *amdgpu_crtc,  in dce_v8_0_program_watermarks()  argument
983 	struct drm_display_mode *mode = &amdgpu_crtc->base.mode;  in dce_v8_0_program_watermarks()
990 	if (amdgpu_crtc->base.enabled && num_heads && mode) {  in dce_v8_0_program_watermarks()
1015 		wm_high.vsc = amdgpu_crtc->vsc;  in dce_v8_0_program_watermarks()
1017 		if (amdgpu_crtc->rmx_type != RMX_OFF)  in dce_v8_0_program_watermarks()
1054 		wm_low.vsc = amdgpu_crtc->vsc;  in dce_v8_0_program_watermarks()
1056 		if (amdgpu_crtc->rmx_type != RMX_OFF)  in dce_v8_0_program_watermarks()
1078 	wm_mask = RREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset);  in dce_v8_0_program_watermarks()
1082 	WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp);  in dce_v8_0_program_watermarks()
1083 	WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset,  in dce_v8_0_program_watermarks()
1087 	tmp = RREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset);  in dce_v8_0_program_watermarks()
1090 	WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp);  in dce_v8_0_program_watermarks()
1091 	WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset,  in dce_v8_0_program_watermarks()
1095 	WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, wm_mask);  in dce_v8_0_program_watermarks()
1098 	amdgpu_crtc->line_time = line_time;  in dce_v8_0_program_watermarks()
1099 	amdgpu_crtc->wm_high = latency_watermark_a;  in dce_v8_0_program_watermarks()
1100 	amdgpu_crtc->wm_low = latency_watermark_b;  in dce_v8_0_program_watermarks()
1102 	amdgpu_crtc->lb_vblank_lead_lines = lb_vblank_lead_lines;  in dce_v8_0_program_watermarks()
1512 	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);  in dce_v8_0_audio_set_dto()  local
1524 …WREG32(mmDCCG_AUDIO_DTO_SOURCE, (amdgpu_crtc->crtc_id << DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO0_SO…  in dce_v8_0_audio_set_dto()
1557 		struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);  in dce_v8_0_afmt_setmode()  local
1558 		bpc = amdgpu_crtc->bpc;  in dce_v8_0_afmt_setmode()
1768 	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);  in dce_v8_0_vga_enable()  local
1773 	vga_control = RREG32(vga_control_regs[amdgpu_crtc->crtc_id]) & ~1;  in dce_v8_0_vga_enable()
1775 		WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control | 1);  in dce_v8_0_vga_enable()
1777 		WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control);  in dce_v8_0_vga_enable()
1782 	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);  in dce_v8_0_grph_enable()  local
1787 		WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, 1);  in dce_v8_0_grph_enable()
1789 		WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, 0);  in dce_v8_0_grph_enable()
1796 	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);  in dce_v8_0_crtc_do_set_base()  local
1952 	WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, 0);  in dce_v8_0_crtc_do_set_base()
1954 	WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,  in dce_v8_0_crtc_do_set_base()
1956 	WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,  in dce_v8_0_crtc_do_set_base()
1958 	WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,  in dce_v8_0_crtc_do_set_base()
1960 	WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,  in dce_v8_0_crtc_do_set_base()
1962 	WREG32(mmGRPH_CONTROL + amdgpu_crtc->crtc_offset, fb_format);  in dce_v8_0_crtc_do_set_base()
1963 	WREG32(mmGRPH_SWAP_CNTL + amdgpu_crtc->crtc_offset, fb_swap);  in dce_v8_0_crtc_do_set_base()
1970 	WREG32_P(mmGRPH_LUT_10BIT_BYPASS_CONTROL + amdgpu_crtc->crtc_offset,  in dce_v8_0_crtc_do_set_base()
1977 	WREG32(mmGRPH_SURFACE_OFFSET_X + amdgpu_crtc->crtc_offset, 0);  in dce_v8_0_crtc_do_set_base()
1978 	WREG32(mmGRPH_SURFACE_OFFSET_Y + amdgpu_crtc->crtc_offset, 0);  in dce_v8_0_crtc_do_set_base()
1979 	WREG32(mmGRPH_X_START + amdgpu_crtc->crtc_offset, 0);  in dce_v8_0_crtc_do_set_base()
1980 	WREG32(mmGRPH_Y_START + amdgpu_crtc->crtc_offset, 0);  in dce_v8_0_crtc_do_set_base()
1981 	WREG32(mmGRPH_X_END + amdgpu_crtc->crtc_offset, target_fb->width);  in dce_v8_0_crtc_do_set_base()
1982 	WREG32(mmGRPH_Y_END + amdgpu_crtc->crtc_offset, target_fb->height);  in dce_v8_0_crtc_do_set_base()
1985 	WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset, fb_pitch_pixels);  in dce_v8_0_crtc_do_set_base()
1989 	WREG32(mmLB_DESKTOP_HEIGHT + amdgpu_crtc->crtc_offset,  in dce_v8_0_crtc_do_set_base()
1994 	WREG32(mmVIEWPORT_START + amdgpu_crtc->crtc_offset,  in dce_v8_0_crtc_do_set_base()
1998 	WREG32(mmVIEWPORT_SIZE + amdgpu_crtc->crtc_offset,  in dce_v8_0_crtc_do_set_base()
2002 	WREG32(mmMASTER_UPDATE_MODE + amdgpu_crtc->crtc_offset, 0);  in dce_v8_0_crtc_do_set_base()
2024 	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);  in dce_v8_0_set_interleave()  local
2027 		WREG32(mmLB_DATA_FORMAT + amdgpu_crtc->crtc_offset,  in dce_v8_0_set_interleave()
2030 		WREG32(mmLB_DATA_FORMAT + amdgpu_crtc->crtc_offset, 0);  in dce_v8_0_set_interleave()
2035 	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);  in dce_v8_0_crtc_load_lut()  local
2041 	DRM_DEBUG_KMS("%d\n", amdgpu_crtc->crtc_id);  in dce_v8_0_crtc_load_lut()
2043 	WREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset,  in dce_v8_0_crtc_load_lut()
2046 	WREG32(mmPRESCALE_GRPH_CONTROL + amdgpu_crtc->crtc_offset,  in dce_v8_0_crtc_load_lut()
2048 	WREG32(mmPRESCALE_OVL_CONTROL + amdgpu_crtc->crtc_offset,  in dce_v8_0_crtc_load_lut()
2050 	WREG32(mmINPUT_GAMMA_CONTROL + amdgpu_crtc->crtc_offset,  in dce_v8_0_crtc_load_lut()
2054 	WREG32(mmDC_LUT_CONTROL + amdgpu_crtc->crtc_offset, 0);  in dce_v8_0_crtc_load_lut()
2056 	WREG32(mmDC_LUT_BLACK_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0);  in dce_v8_0_crtc_load_lut()
2057 	WREG32(mmDC_LUT_BLACK_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0);  in dce_v8_0_crtc_load_lut()
2058 	WREG32(mmDC_LUT_BLACK_OFFSET_RED + amdgpu_crtc->crtc_offset, 0);  in dce_v8_0_crtc_load_lut()
2060 	WREG32(mmDC_LUT_WHITE_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0xffff);  in dce_v8_0_crtc_load_lut()
2061 	WREG32(mmDC_LUT_WHITE_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0xffff);  in dce_v8_0_crtc_load_lut()
2062 	WREG32(mmDC_LUT_WHITE_OFFSET_RED + amdgpu_crtc->crtc_offset, 0xffff);  in dce_v8_0_crtc_load_lut()
2064 	WREG32(mmDC_LUT_RW_MODE + amdgpu_crtc->crtc_offset, 0);  in dce_v8_0_crtc_load_lut()
2065 	WREG32(mmDC_LUT_WRITE_EN_MASK + amdgpu_crtc->crtc_offset, 0x00000007);  in dce_v8_0_crtc_load_lut()
2067 	WREG32(mmDC_LUT_RW_INDEX + amdgpu_crtc->crtc_offset, 0);  in dce_v8_0_crtc_load_lut()
2072 		WREG32(mmDC_LUT_30_COLOR + amdgpu_crtc->crtc_offset,  in dce_v8_0_crtc_load_lut()
2078 	WREG32(mmDEGAMMA_CONTROL + amdgpu_crtc->crtc_offset,  in dce_v8_0_crtc_load_lut()
2082 	WREG32(mmGAMUT_REMAP_CONTROL + amdgpu_crtc->crtc_offset,  in dce_v8_0_crtc_load_lut()
2085 	WREG32(mmREGAMMA_CONTROL + amdgpu_crtc->crtc_offset,  in dce_v8_0_crtc_load_lut()
2088 	WREG32(mmOUTPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset,  in dce_v8_0_crtc_load_lut()
2092 	WREG32(0x1a50 + amdgpu_crtc->crtc_offset, 0);  in dce_v8_0_crtc_load_lut()
2096 	WREG32(mmALPHA_CONTROL + amdgpu_crtc->crtc_offset,  in dce_v8_0_crtc_load_lut()
2153 	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);  in dce_v8_0_pick_pll()  local
2159 	if (ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder))) {  in dce_v8_0_pick_pll()
2204 	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);  in dce_v8_0_lock_cursor()  local
2207 	cur_lock = RREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset);  in dce_v8_0_lock_cursor()
2212 	WREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset, cur_lock);  in dce_v8_0_lock_cursor()
2217 	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);  in dce_v8_0_hide_cursor()  local
2220 	WREG32(mmCUR_CONTROL + amdgpu_crtc->crtc_offset,  in dce_v8_0_hide_cursor()
2227 	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);  in dce_v8_0_show_cursor()  local
2230 	WREG32(mmCUR_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,  in dce_v8_0_show_cursor()
2231 	       upper_32_bits(amdgpu_crtc->cursor_addr));  in dce_v8_0_show_cursor()
2232 	WREG32(mmCUR_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,  in dce_v8_0_show_cursor()
2233 	       lower_32_bits(amdgpu_crtc->cursor_addr));  in dce_v8_0_show_cursor()
2235 	WREG32(mmCUR_CONTROL + amdgpu_crtc->crtc_offset,  in dce_v8_0_show_cursor()
2244 	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);  in dce_v8_0_cursor_move_locked()  local
2248 	amdgpu_crtc->cursor_x = x;  in dce_v8_0_cursor_move_locked()
2249 	amdgpu_crtc->cursor_y = y;  in dce_v8_0_cursor_move_locked()
2257 		xorigin = min(-x, amdgpu_crtc->max_cursor_width - 1);  in dce_v8_0_cursor_move_locked()
2261 		yorigin = min(-y, amdgpu_crtc->max_cursor_height - 1);  in dce_v8_0_cursor_move_locked()
2265 	WREG32(mmCUR_POSITION + amdgpu_crtc->crtc_offset, (x << 16) | y);  in dce_v8_0_cursor_move_locked()
2266 	WREG32(mmCUR_HOT_SPOT + amdgpu_crtc->crtc_offset, (xorigin << 16) | yorigin);  in dce_v8_0_cursor_move_locked()
2267 	WREG32(mmCUR_SIZE + amdgpu_crtc->crtc_offset,  in dce_v8_0_cursor_move_locked()
2268 	       ((amdgpu_crtc->cursor_width - 1) << 16) | (amdgpu_crtc->cursor_height - 1));  in dce_v8_0_cursor_move_locked()
2293 	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);  in dce_v8_0_crtc_cursor_set2()  local
2305 	if ((width > amdgpu_crtc->max_cursor_width) ||  in dce_v8_0_crtc_cursor_set2()
2306 	    (height > amdgpu_crtc->max_cursor_height)) {  in dce_v8_0_crtc_cursor_set2()
2313 		DRM_ERROR("Cannot find cursor object %x for crtc %d\n", handle, amdgpu_crtc->crtc_id);  in dce_v8_0_crtc_cursor_set2()
2332 	amdgpu_crtc->cursor_addr = amdgpu_bo_gpu_offset(aobj);  in dce_v8_0_crtc_cursor_set2()
2336 	if (width != amdgpu_crtc->cursor_width ||  in dce_v8_0_crtc_cursor_set2()
2337 	    height != amdgpu_crtc->cursor_height ||  in dce_v8_0_crtc_cursor_set2()
2338 	    hot_x != amdgpu_crtc->cursor_hot_x ||  in dce_v8_0_crtc_cursor_set2()
2339 	    hot_y != amdgpu_crtc->cursor_hot_y) {  in dce_v8_0_crtc_cursor_set2()
2342 		x = amdgpu_crtc->cursor_x + amdgpu_crtc->cursor_hot_x - hot_x;  in dce_v8_0_crtc_cursor_set2()
2343 		y = amdgpu_crtc->cursor_y + amdgpu_crtc->cursor_hot_y - hot_y;  in dce_v8_0_crtc_cursor_set2()
2347 		amdgpu_crtc->cursor_width = width;  in dce_v8_0_crtc_cursor_set2()
2348 		amdgpu_crtc->cursor_height = height;  in dce_v8_0_crtc_cursor_set2()
2349 		amdgpu_crtc->cursor_hot_x = hot_x;  in dce_v8_0_crtc_cursor_set2()
2350 		amdgpu_crtc->cursor_hot_y = hot_y;  in dce_v8_0_crtc_cursor_set2()
2357 	if (amdgpu_crtc->cursor_bo) {  in dce_v8_0_crtc_cursor_set2()
2358 		struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo);  in dce_v8_0_crtc_cursor_set2()
2364 		drm_gem_object_put(amdgpu_crtc->cursor_bo);  in dce_v8_0_crtc_cursor_set2()
2367 	amdgpu_crtc->cursor_bo = obj;  in dce_v8_0_crtc_cursor_set2()
2373 	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);  in dce_v8_0_cursor_reset()  local
2375 	if (amdgpu_crtc->cursor_bo) {  in dce_v8_0_cursor_reset()
2378 		dce_v8_0_cursor_move_locked(crtc, amdgpu_crtc->cursor_x,  in dce_v8_0_cursor_reset()
2379 					    amdgpu_crtc->cursor_y);  in dce_v8_0_cursor_reset()
2398 	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);  in dce_v8_0_crtc_destroy()  local
2401 	kfree(amdgpu_crtc);  in dce_v8_0_crtc_destroy()
2421 	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);  in dce_v8_0_crtc_dpms()  local
2426 		amdgpu_crtc->enabled = true;  in dce_v8_0_crtc_dpms()
2433 						amdgpu_crtc->crtc_id);  in dce_v8_0_crtc_dpms()
2443 		if (amdgpu_crtc->enabled) {  in dce_v8_0_crtc_dpms()
2449 		amdgpu_crtc->enabled = false;  in dce_v8_0_crtc_dpms()
2472 	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);  in dce_v8_0_crtc_disable()  local
2500 		    i != amdgpu_crtc->crtc_id &&  in dce_v8_0_crtc_disable()
2501 		    amdgpu_crtc->pll_id == adev->mode_info.crtcs[i]->pll_id) {  in dce_v8_0_crtc_disable()
2509 	switch (amdgpu_crtc->pll_id) {  in dce_v8_0_crtc_disable()
2513 		amdgpu_atombios_crtc_program_pll(crtc, amdgpu_crtc->crtc_id, amdgpu_crtc->pll_id,  in dce_v8_0_crtc_disable()
2521 			amdgpu_atombios_crtc_program_pll(crtc, amdgpu_crtc->crtc_id, amdgpu_crtc->pll_id,  in dce_v8_0_crtc_disable()
2528 	amdgpu_crtc->pll_id = ATOM_PPLL_INVALID;  in dce_v8_0_crtc_disable()
2529 	amdgpu_crtc->adjusted_clock = 0;  in dce_v8_0_crtc_disable()
2530 	amdgpu_crtc->encoder = NULL;  in dce_v8_0_crtc_disable()
2531 	amdgpu_crtc->connector = NULL;  in dce_v8_0_crtc_disable()
2539 	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);  in dce_v8_0_crtc_mode_set()  local
2541 	if (!amdgpu_crtc->adjusted_clock)  in dce_v8_0_crtc_mode_set()
2551 	amdgpu_crtc->hw_mode = *adjusted_mode;  in dce_v8_0_crtc_mode_set()
2560 	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);  in dce_v8_0_crtc_mode_fixup()  local
2567 			amdgpu_crtc->encoder = encoder;  in dce_v8_0_crtc_mode_fixup()
2568 			amdgpu_crtc->connector = amdgpu_get_connector_for_encoder(encoder);  in dce_v8_0_crtc_mode_fixup()
2572 	if ((amdgpu_crtc->encoder == NULL) || (amdgpu_crtc->connector == NULL)) {  in dce_v8_0_crtc_mode_fixup()
2573 		amdgpu_crtc->encoder = NULL;  in dce_v8_0_crtc_mode_fixup()
2574 		amdgpu_crtc->connector = NULL;  in dce_v8_0_crtc_mode_fixup()
2582 	amdgpu_crtc->pll_id = dce_v8_0_pick_pll(crtc);  in dce_v8_0_crtc_mode_fixup()
2584 	if ((amdgpu_crtc->pll_id == ATOM_PPLL_INVALID) &&  in dce_v8_0_crtc_mode_fixup()
2585 	    !ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder)))  in dce_v8_0_crtc_mode_fixup()
2619 	struct amdgpu_crtc *amdgpu_crtc;  in dce_v8_0_panic_flush()  local
2627 	amdgpu_crtc = to_amdgpu_crtc(plane->crtc);  in dce_v8_0_panic_flush()
2631 	fb_format = RREG32(mmGRPH_CONTROL + amdgpu_crtc->crtc_offset);  in dce_v8_0_panic_flush()
2633 	WREG32(mmGRPH_CONTROL + amdgpu_crtc->crtc_offset, fb_format);  in dce_v8_0_panic_flush()
2643 	struct amdgpu_crtc *amdgpu_crtc;  in dce_v8_0_crtc_init()  local
2645 	amdgpu_crtc = kzalloc(sizeof(struct amdgpu_crtc) +  in dce_v8_0_crtc_init()
2647 	if (amdgpu_crtc == NULL)  in dce_v8_0_crtc_init()
2650 	drm_crtc_init(adev_to_drm(adev), &amdgpu_crtc->base, &dce_v8_0_crtc_funcs);  in dce_v8_0_crtc_init()
2652 	drm_mode_crtc_set_gamma_size(&amdgpu_crtc->base, 256);  in dce_v8_0_crtc_init()
2653 	amdgpu_crtc->crtc_id = index;  in dce_v8_0_crtc_init()
2654 	adev->mode_info.crtcs[index] = amdgpu_crtc;  in dce_v8_0_crtc_init()
2656 	amdgpu_crtc->max_cursor_width = CIK_CURSOR_WIDTH;  in dce_v8_0_crtc_init()
2657 	amdgpu_crtc->max_cursor_height = CIK_CURSOR_HEIGHT;  in dce_v8_0_crtc_init()
2658 	adev_to_drm(adev)->mode_config.cursor_width = amdgpu_crtc->max_cursor_width;  in dce_v8_0_crtc_init()
2659 	adev_to_drm(adev)->mode_config.cursor_height = amdgpu_crtc->max_cursor_height;  in dce_v8_0_crtc_init()
2661 	amdgpu_crtc->crtc_offset = crtc_offsets[amdgpu_crtc->crtc_id];  in dce_v8_0_crtc_init()
2663 	amdgpu_crtc->pll_id = ATOM_PPLL_INVALID;  in dce_v8_0_crtc_init()
2664 	amdgpu_crtc->adjusted_clock = 0;  in dce_v8_0_crtc_init()
2665 	amdgpu_crtc->encoder = NULL;  in dce_v8_0_crtc_init()
2666 	amdgpu_crtc->connector = NULL;  in dce_v8_0_crtc_init()
2667 	drm_crtc_helper_add(&amdgpu_crtc->base, &dce_v8_0_crtc_helper_funcs);  in dce_v8_0_crtc_init()
2668 	drm_plane_helper_add(amdgpu_crtc->base.primary, &dce_v8_0_drm_primary_plane_helper_funcs);  in dce_v8_0_crtc_init()
3168 	struct amdgpu_crtc *amdgpu_crtc;  in dce_v8_0_pageflip_irq()  local
3172 	amdgpu_crtc = adev->mode_info.crtcs[crtc_id];  in dce_v8_0_pageflip_irq()
3185 	if (amdgpu_crtc == NULL)  in dce_v8_0_pageflip_irq()
3189 	works = amdgpu_crtc->pflip_works;  in dce_v8_0_pageflip_irq()
3190 	if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_SUBMITTED) {  in dce_v8_0_pageflip_irq()
3193 						amdgpu_crtc->pflip_status,  in dce_v8_0_pageflip_irq()
3200 	amdgpu_crtc->pflip_status = AMDGPU_FLIP_NONE;  in dce_v8_0_pageflip_irq()
3201 	amdgpu_crtc->pflip_works = NULL;  in dce_v8_0_pageflip_irq()
3205 		drm_crtc_send_vblank_event(&amdgpu_crtc->base, works->event);  in dce_v8_0_pageflip_irq()
3209 	drm_crtc_vblank_put(&amdgpu_crtc->base);  in dce_v8_0_pageflip_irq()