163 	if (crtc >= adev->mode_info.num_crtc)  in dce_v6_0_vblank_get_counter()
174 	for (i = 0; i < adev->mode_info.num_crtc; i++)  in dce_v6_0_pageflip_interrupt_init()
183 	for (i = 0; i < adev->mode_info.num_crtc; i++)  in dce_v6_0_pageflip_interrupt_fini()
226 	if ((crtc < 0) || (crtc >= adev->mode_info.num_crtc))  in dce_v6_0_crtc_get_scanoutpos()
387 	for (i = 0; i < adev->mode_info.num_crtc; i++) {  in dce_v6_0_is_display_hung()
395 		for (i = 0; i < adev->mode_info.num_crtc; i++) {  in dce_v6_0_is_display_hung()
1138 	for (i = 0; i < adev->mode_info.num_crtc; i++) {  in dce_v6_0_bandwidth_update()
1142 	for (i = 0; i < adev->mode_info.num_crtc; i += 2) {  in dce_v6_0_bandwidth_update()
2544 	for (i = 0; i < adev->mode_info.num_crtc; i++) {  in dce_v6_0_crtc_disable()
2723 	adev->mode_info.num_crtc = dce_v6_0_get_num_crtc(adev);  in dce_v6_0_early_init()
2751 	for (i = 0; i < adev->mode_info.num_crtc; i++) {  in dce_v6_0_sw_init()
2786 	for (i = 0; i < adev->mode_info.num_crtc; i++) {  in dce_v6_0_sw_init()
2811 	r = drm_vblank_init(adev_to_drm(adev), adev->mode_info.num_crtc);  in dce_v6_0_sw_init()
2957 	if (crtc >= adev->mode_info.num_crtc) {  in dce_v6_0_set_crtc_vblank_interrupt_state()
3131 	if (type >= adev->mode_info.num_crtc) {  in dce_v6_0_set_pageflip_interrupt_state()
3159 	if (crtc_id >= adev->mode_info.num_crtc) {  in dce_v6_0_pageflip_irq()
3446 	switch (adev->mode_info.num_crtc) {  in dce_v6_0_encoder_add()
3560 	if (adev->mode_info.num_crtc > 0)  in dce_v6_0_set_irq_funcs()
3561 		adev->crtc_irq.num_types = AMDGPU_CRTC_IRQ_VLINE1 + adev->mode_info.num_crtc;  in dce_v6_0_set_irq_funcs()
3566 	adev->pageflip_irq.num_types = adev->mode_info.num_crtc;  in dce_v6_0_set_irq_funcs()