77 static const u32 hpd_offsets[] =  variable
252 	if (RREG32(mmDC_HPD1_INT_STATUS + hpd_offsets[hpd]) &  in dce_v6_0_hpd_sense()
276 	tmp = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd]);  in dce_v6_0_hpd_set_polarity()
281 	WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd], tmp);  in dce_v6_0_hpd_set_polarity()
294 	tmp = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd]);  in dce_v6_0_hpd_int_ack()
296 	WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd], tmp);  in dce_v6_0_hpd_int_ack()
321 		tmp = RREG32(mmDC_HPD1_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]);  in dce_v6_0_hpd_init()
323 		WREG32(mmDC_HPD1_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);  in dce_v6_0_hpd_init()
332 			tmp = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]);  in dce_v6_0_hpd_init()
334 			WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);  in dce_v6_0_hpd_init()
367 		tmp = RREG32(mmDC_HPD1_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]);  in dce_v6_0_hpd_fini()
369 		WREG32(mmDC_HPD1_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);  in dce_v6_0_hpd_fini()
3023 		dc_hpd_int_cntl = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[type]);  in dce_v6_0_set_hpd_interrupt_state()
3025 		WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[type], dc_hpd_int_cntl);  in dce_v6_0_set_hpd_interrupt_state()
3028 		dc_hpd_int_cntl = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[type]);  in dce_v6_0_set_hpd_interrupt_state()
3030 		WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[type], dc_hpd_int_cntl);  in dce_v6_0_set_hpd_interrupt_state()