204 	struct amdgpu_crtc *amdgpu_crtc = adev->mode_info.crtcs[crtc_id];  in dce_v6_0_page_flip()  local
205 	struct drm_framebuffer *fb = amdgpu_crtc->base.primary->fb;  in dce_v6_0_page_flip()
208 	WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, async ?  in dce_v6_0_page_flip()
211 	WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset,  in dce_v6_0_page_flip()
214 	WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,  in dce_v6_0_page_flip()
217 	WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,  in dce_v6_0_page_flip()
220 	RREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset);  in dce_v6_0_page_flip()
462 	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);  in dce_v6_0_program_fmt()  local
509 	WREG32(mmFMT_BIT_DEPTH_CONTROL + amdgpu_crtc->crtc_offset, tmp);  in dce_v6_0_program_fmt()
880 					struct amdgpu_crtc *amdgpu_crtc,  in dce_v6_0_program_watermarks()  argument
883 	struct drm_display_mode *mode = &amdgpu_crtc->base.mode;  in dce_v6_0_program_watermarks()
895 	if (amdgpu_crtc->base.enabled && num_heads && mode) {  in dce_v6_0_program_watermarks()
924 		wm_high.vsc = amdgpu_crtc->vsc;  in dce_v6_0_program_watermarks()
926 		if (amdgpu_crtc->rmx_type != RMX_OFF)  in dce_v6_0_program_watermarks()
951 		wm_low.vsc = amdgpu_crtc->vsc;  in dce_v6_0_program_watermarks()
953 		if (amdgpu_crtc->rmx_type != RMX_OFF)  in dce_v6_0_program_watermarks()
989 		c.full = dfixed_mul(c, amdgpu_crtc->hsc);  in dce_v6_0_program_watermarks()
1001 		c.full = dfixed_mul(c, amdgpu_crtc->hsc);  in dce_v6_0_program_watermarks()
1012 	arb_control3 = RREG32(mmDPG_PIPE_ARBITRATION_CONTROL3 + amdgpu_crtc->crtc_offset);  in dce_v6_0_program_watermarks()
1016 	WREG32(mmDPG_PIPE_ARBITRATION_CONTROL3 + amdgpu_crtc->crtc_offset, tmp);  in dce_v6_0_program_watermarks()
1017 	WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset,  in dce_v6_0_program_watermarks()
1021 	tmp = RREG32(mmDPG_PIPE_ARBITRATION_CONTROL3 + amdgpu_crtc->crtc_offset);  in dce_v6_0_program_watermarks()
1024 	WREG32(mmDPG_PIPE_ARBITRATION_CONTROL3 + amdgpu_crtc->crtc_offset, tmp);  in dce_v6_0_program_watermarks()
1025 	WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset,  in dce_v6_0_program_watermarks()
1029 	WREG32(mmDPG_PIPE_ARBITRATION_CONTROL3 + amdgpu_crtc->crtc_offset, arb_control3);  in dce_v6_0_program_watermarks()
1032 	WREG32(mmPRIORITY_A_CNT + amdgpu_crtc->crtc_offset, priority_a_cnt);  in dce_v6_0_program_watermarks()
1033 	WREG32(mmPRIORITY_B_CNT + amdgpu_crtc->crtc_offset, priority_b_cnt);  in dce_v6_0_program_watermarks()
1036 	amdgpu_crtc->line_time = line_time;  in dce_v6_0_program_watermarks()
1037 	amdgpu_crtc->wm_high = latency_watermark_a;  in dce_v6_0_program_watermarks()
1040 	amdgpu_crtc->lb_vblank_lead_lines = lb_vblank_lead_lines;  in dce_v6_0_program_watermarks()
1059 				   struct amdgpu_crtc *amdgpu_crtc,  in dce_v6_0_line_buffer_adjust()  argument
1064 	u32 pipe_offset = amdgpu_crtc->crtc_id * 0x8;  in dce_v6_0_line_buffer_adjust()
1078 	if (amdgpu_crtc->base.enabled && mode) {  in dce_v6_0_line_buffer_adjust()
1091 	WREG32(mmDC_LB_MEMORY_SPLIT + amdgpu_crtc->crtc_offset,  in dce_v6_0_line_buffer_adjust()
1103 	if (amdgpu_crtc->base.enabled && mode) {  in dce_v6_0_line_buffer_adjust()
1562 	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);  in dce_v6_0_audio_set_dto()  local
1574 			DCCG_AUDIO_DTO0_SOURCE_SEL, amdgpu_crtc->crtc_id);  in dce_v6_0_audio_set_dto()
1752 		struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);  in dce_v6_0_afmt_setmode()  local
1753 		bpc = amdgpu_crtc->bpc;  in dce_v6_0_afmt_setmode()
1859 	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);  in dce_v6_0_vga_enable()  local
1864 	vga_control = RREG32(vga_control_regs[amdgpu_crtc->crtc_id]) & ~1;  in dce_v6_0_vga_enable()
1865 	WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control | (enable ? 1 : 0));  in dce_v6_0_vga_enable()
1870 	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);  in dce_v6_0_grph_enable()  local
1874 	WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, enable ? 1 : 0);  in dce_v6_0_grph_enable()
1881 	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);  in dce_v6_0_crtc_do_set_base()  local
2034 	WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, 0);  in dce_v6_0_crtc_do_set_base()
2036 	WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,  in dce_v6_0_crtc_do_set_base()
2038 	WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,  in dce_v6_0_crtc_do_set_base()
2040 	WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,  in dce_v6_0_crtc_do_set_base()
2042 	WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,  in dce_v6_0_crtc_do_set_base()
2044 	WREG32(mmGRPH_CONTROL + amdgpu_crtc->crtc_offset, fb_format);  in dce_v6_0_crtc_do_set_base()
2045 	WREG32(mmGRPH_SWAP_CNTL + amdgpu_crtc->crtc_offset, fb_swap);  in dce_v6_0_crtc_do_set_base()
2052 	WREG32_P(mmGRPH_LUT_10BIT_BYPASS + amdgpu_crtc->crtc_offset,  in dce_v6_0_crtc_do_set_base()
2059 	WREG32(mmGRPH_SURFACE_OFFSET_X + amdgpu_crtc->crtc_offset, 0);  in dce_v6_0_crtc_do_set_base()
2060 	WREG32(mmGRPH_SURFACE_OFFSET_Y + amdgpu_crtc->crtc_offset, 0);  in dce_v6_0_crtc_do_set_base()
2061 	WREG32(mmGRPH_X_START + amdgpu_crtc->crtc_offset, 0);  in dce_v6_0_crtc_do_set_base()
2062 	WREG32(mmGRPH_Y_START + amdgpu_crtc->crtc_offset, 0);  in dce_v6_0_crtc_do_set_base()
2063 	WREG32(mmGRPH_X_END + amdgpu_crtc->crtc_offset, target_fb->width);  in dce_v6_0_crtc_do_set_base()
2064 	WREG32(mmGRPH_Y_END + amdgpu_crtc->crtc_offset, target_fb->height);  in dce_v6_0_crtc_do_set_base()
2067 	WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset, fb_pitch_pixels);  in dce_v6_0_crtc_do_set_base()
2071 	WREG32(mmDESKTOP_HEIGHT + amdgpu_crtc->crtc_offset,  in dce_v6_0_crtc_do_set_base()
2075 	WREG32(mmVIEWPORT_START + amdgpu_crtc->crtc_offset,  in dce_v6_0_crtc_do_set_base()
2080 	WREG32(mmVIEWPORT_SIZE + amdgpu_crtc->crtc_offset,  in dce_v6_0_crtc_do_set_base()
2084 	WREG32(mmMASTER_UPDATE_MODE + amdgpu_crtc->crtc_offset, 0);  in dce_v6_0_crtc_do_set_base()
2107 	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);  in dce_v6_0_set_interleave()  local
2110 		WREG32(mmDATA_FORMAT + amdgpu_crtc->crtc_offset,  in dce_v6_0_set_interleave()
2113 		WREG32(mmDATA_FORMAT + amdgpu_crtc->crtc_offset, 0);  in dce_v6_0_set_interleave()
2119 	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);  in dce_v6_0_crtc_load_lut()  local
2125 	DRM_DEBUG_KMS("%d\n", amdgpu_crtc->crtc_id);  in dce_v6_0_crtc_load_lut()
2127 	WREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset,  in dce_v6_0_crtc_load_lut()
2130 	WREG32(mmPRESCALE_GRPH_CONTROL + amdgpu_crtc->crtc_offset,  in dce_v6_0_crtc_load_lut()
2132 	WREG32(mmPRESCALE_OVL_CONTROL + amdgpu_crtc->crtc_offset,  in dce_v6_0_crtc_load_lut()
2134 	WREG32(mmINPUT_GAMMA_CONTROL + amdgpu_crtc->crtc_offset,  in dce_v6_0_crtc_load_lut()
2138 	WREG32(mmDC_LUT_CONTROL + amdgpu_crtc->crtc_offset, 0);  in dce_v6_0_crtc_load_lut()
2140 	WREG32(mmDC_LUT_BLACK_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0);  in dce_v6_0_crtc_load_lut()
2141 	WREG32(mmDC_LUT_BLACK_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0);  in dce_v6_0_crtc_load_lut()
2142 	WREG32(mmDC_LUT_BLACK_OFFSET_RED + amdgpu_crtc->crtc_offset, 0);  in dce_v6_0_crtc_load_lut()
2144 	WREG32(mmDC_LUT_WHITE_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0xffff);  in dce_v6_0_crtc_load_lut()
2145 	WREG32(mmDC_LUT_WHITE_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0xffff);  in dce_v6_0_crtc_load_lut()
2146 	WREG32(mmDC_LUT_WHITE_OFFSET_RED + amdgpu_crtc->crtc_offset, 0xffff);  in dce_v6_0_crtc_load_lut()
2148 	WREG32(mmDC_LUT_RW_MODE + amdgpu_crtc->crtc_offset, 0);  in dce_v6_0_crtc_load_lut()
2149 	WREG32(mmDC_LUT_WRITE_EN_MASK + amdgpu_crtc->crtc_offset, 0x00000007);  in dce_v6_0_crtc_load_lut()
2151 	WREG32(mmDC_LUT_RW_INDEX + amdgpu_crtc->crtc_offset, 0);  in dce_v6_0_crtc_load_lut()
2156 		WREG32(mmDC_LUT_30_COLOR + amdgpu_crtc->crtc_offset,  in dce_v6_0_crtc_load_lut()
2162 	WREG32(mmDEGAMMA_CONTROL + amdgpu_crtc->crtc_offset,  in dce_v6_0_crtc_load_lut()
2167 	WREG32(mmGAMUT_REMAP_CONTROL + amdgpu_crtc->crtc_offset,  in dce_v6_0_crtc_load_lut()
2170 	WREG32(mmREGAMMA_CONTROL + amdgpu_crtc->crtc_offset,  in dce_v6_0_crtc_load_lut()
2173 	WREG32(mmOUTPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset,  in dce_v6_0_crtc_load_lut()
2177 	WREG32(0x1a50 + amdgpu_crtc->crtc_offset, 0);  in dce_v6_0_crtc_load_lut()
2219 	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);  in dce_v6_0_pick_pll()  local
2225 	if (ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder))) {  in dce_v6_0_pick_pll()
2251 	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);  in dce_v6_0_lock_cursor()  local
2254 	cur_lock = RREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset);  in dce_v6_0_lock_cursor()
2259 	WREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset, cur_lock);  in dce_v6_0_lock_cursor()
2264 	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);  in dce_v6_0_hide_cursor()  local
2267 	WREG32(mmCUR_CONTROL + amdgpu_crtc->crtc_offset,  in dce_v6_0_hide_cursor()
2276 	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);  in dce_v6_0_show_cursor()  local
2279 	WREG32(mmCUR_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,  in dce_v6_0_show_cursor()
2280 	       upper_32_bits(amdgpu_crtc->cursor_addr));  in dce_v6_0_show_cursor()
2281 	WREG32(mmCUR_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,  in dce_v6_0_show_cursor()
2282 	       lower_32_bits(amdgpu_crtc->cursor_addr));  in dce_v6_0_show_cursor()
2284 	WREG32(mmCUR_CONTROL + amdgpu_crtc->crtc_offset,  in dce_v6_0_show_cursor()
2294 	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);  in dce_v6_0_cursor_move_locked()  local
2298 	int w = amdgpu_crtc->cursor_width;  in dce_v6_0_cursor_move_locked()
2300 	amdgpu_crtc->cursor_x = x;  in dce_v6_0_cursor_move_locked()
2301 	amdgpu_crtc->cursor_y = y;  in dce_v6_0_cursor_move_locked()
2309 		xorigin = min(-x, amdgpu_crtc->max_cursor_width - 1);  in dce_v6_0_cursor_move_locked()
2313 		yorigin = min(-y, amdgpu_crtc->max_cursor_height - 1);  in dce_v6_0_cursor_move_locked()
2317 	WREG32(mmCUR_POSITION + amdgpu_crtc->crtc_offset, (x << 16) | y);  in dce_v6_0_cursor_move_locked()
2318 	WREG32(mmCUR_HOT_SPOT + amdgpu_crtc->crtc_offset, (xorigin << 16) | yorigin);  in dce_v6_0_cursor_move_locked()
2319 	WREG32(mmCUR_SIZE + amdgpu_crtc->crtc_offset,  in dce_v6_0_cursor_move_locked()
2320 	       ((w - 1) << 16) | (amdgpu_crtc->cursor_height - 1));  in dce_v6_0_cursor_move_locked()
2345 	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);  in dce_v6_0_crtc_cursor_set2()  local
2357 	if ((width > amdgpu_crtc->max_cursor_width) ||  in dce_v6_0_crtc_cursor_set2()
2358 	    (height > amdgpu_crtc->max_cursor_height)) {  in dce_v6_0_crtc_cursor_set2()
2365 		DRM_ERROR("Cannot find cursor object %x for crtc %d\n", handle, amdgpu_crtc->crtc_id);  in dce_v6_0_crtc_cursor_set2()
2384 	amdgpu_crtc->cursor_addr = amdgpu_bo_gpu_offset(aobj);  in dce_v6_0_crtc_cursor_set2()
2388 	if (width != amdgpu_crtc->cursor_width ||  in dce_v6_0_crtc_cursor_set2()
2389 	    height != amdgpu_crtc->cursor_height ||  in dce_v6_0_crtc_cursor_set2()
2390 	    hot_x != amdgpu_crtc->cursor_hot_x ||  in dce_v6_0_crtc_cursor_set2()
2391 	    hot_y != amdgpu_crtc->cursor_hot_y) {  in dce_v6_0_crtc_cursor_set2()
2394 		x = amdgpu_crtc->cursor_x + amdgpu_crtc->cursor_hot_x - hot_x;  in dce_v6_0_crtc_cursor_set2()
2395 		y = amdgpu_crtc->cursor_y + amdgpu_crtc->cursor_hot_y - hot_y;  in dce_v6_0_crtc_cursor_set2()
2399 		amdgpu_crtc->cursor_width = width;  in dce_v6_0_crtc_cursor_set2()
2400 		amdgpu_crtc->cursor_height = height;  in dce_v6_0_crtc_cursor_set2()
2401 		amdgpu_crtc->cursor_hot_x = hot_x;  in dce_v6_0_crtc_cursor_set2()
2402 		amdgpu_crtc->cursor_hot_y = hot_y;  in dce_v6_0_crtc_cursor_set2()
2409 	if (amdgpu_crtc->cursor_bo) {  in dce_v6_0_crtc_cursor_set2()
2410 		struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo);  in dce_v6_0_crtc_cursor_set2()
2416 		drm_gem_object_put(amdgpu_crtc->cursor_bo);  in dce_v6_0_crtc_cursor_set2()
2419 	amdgpu_crtc->cursor_bo = obj;  in dce_v6_0_crtc_cursor_set2()
2425 	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);  in dce_v6_0_cursor_reset()  local
2427 	if (amdgpu_crtc->cursor_bo) {  in dce_v6_0_cursor_reset()
2430 		dce_v6_0_cursor_move_locked(crtc, amdgpu_crtc->cursor_x,  in dce_v6_0_cursor_reset()
2431 					    amdgpu_crtc->cursor_y);  in dce_v6_0_cursor_reset()
2449 	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);  in dce_v6_0_crtc_destroy()  local
2452 	kfree(amdgpu_crtc);  in dce_v6_0_crtc_destroy()
2472 	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);  in dce_v6_0_crtc_dpms()  local
2477 		amdgpu_crtc->enabled = true;  in dce_v6_0_crtc_dpms()
2482 						amdgpu_crtc->crtc_id);  in dce_v6_0_crtc_dpms()
2492 		if (amdgpu_crtc->enabled)  in dce_v6_0_crtc_dpms()
2495 		amdgpu_crtc->enabled = false;  in dce_v6_0_crtc_dpms()
2519 	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);  in dce_v6_0_crtc_disable()  local
2547 		    i != amdgpu_crtc->crtc_id &&  in dce_v6_0_crtc_disable()
2548 		    amdgpu_crtc->pll_id == adev->mode_info.crtcs[i]->pll_id) {  in dce_v6_0_crtc_disable()
2556 	switch (amdgpu_crtc->pll_id) {  in dce_v6_0_crtc_disable()
2560 		amdgpu_atombios_crtc_program_pll(crtc, amdgpu_crtc->crtc_id, amdgpu_crtc->pll_id,  in dce_v6_0_crtc_disable()
2567 	amdgpu_crtc->pll_id = ATOM_PPLL_INVALID;  in dce_v6_0_crtc_disable()
2568 	amdgpu_crtc->adjusted_clock = 0;  in dce_v6_0_crtc_disable()
2569 	amdgpu_crtc->encoder = NULL;  in dce_v6_0_crtc_disable()
2570 	amdgpu_crtc->connector = NULL;  in dce_v6_0_crtc_disable()
2578 	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);  in dce_v6_0_crtc_mode_set()  local
2580 	if (!amdgpu_crtc->adjusted_clock)  in dce_v6_0_crtc_mode_set()
2590 	amdgpu_crtc->hw_mode = *adjusted_mode;  in dce_v6_0_crtc_mode_set()
2600 	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);  in dce_v6_0_crtc_mode_fixup()  local
2607 			amdgpu_crtc->encoder = encoder;  in dce_v6_0_crtc_mode_fixup()
2608 			amdgpu_crtc->connector = amdgpu_get_connector_for_encoder(encoder);  in dce_v6_0_crtc_mode_fixup()
2612 	if ((amdgpu_crtc->encoder == NULL) || (amdgpu_crtc->connector == NULL)) {  in dce_v6_0_crtc_mode_fixup()
2613 		amdgpu_crtc->encoder = NULL;  in dce_v6_0_crtc_mode_fixup()
2614 		amdgpu_crtc->connector = NULL;  in dce_v6_0_crtc_mode_fixup()
2622 	amdgpu_crtc->pll_id = dce_v6_0_pick_pll(crtc);  in dce_v6_0_crtc_mode_fixup()
2624 	if ((amdgpu_crtc->pll_id == ATOM_PPLL_INVALID) &&  in dce_v6_0_crtc_mode_fixup()
2625 	    !ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder)))  in dce_v6_0_crtc_mode_fixup()
2659 	struct amdgpu_crtc *amdgpu_crtc;  in dce_v6_0_panic_flush()  local
2667 	amdgpu_crtc = to_amdgpu_crtc(plane->crtc);  in dce_v6_0_panic_flush()
2671 	fb_format = RREG32(mmGRPH_CONTROL + amdgpu_crtc->crtc_offset);  in dce_v6_0_panic_flush()
2673 	WREG32(mmGRPH_CONTROL + amdgpu_crtc->crtc_offset, fb_format);  in dce_v6_0_panic_flush()
2684 	struct amdgpu_crtc *amdgpu_crtc;  in dce_v6_0_crtc_init()  local
2686 	amdgpu_crtc = kzalloc(sizeof(struct amdgpu_crtc) +  in dce_v6_0_crtc_init()
2688 	if (amdgpu_crtc == NULL)  in dce_v6_0_crtc_init()
2691 	drm_crtc_init(adev_to_drm(adev), &amdgpu_crtc->base, &dce_v6_0_crtc_funcs);  in dce_v6_0_crtc_init()
2693 	drm_mode_crtc_set_gamma_size(&amdgpu_crtc->base, 256);  in dce_v6_0_crtc_init()
2694 	amdgpu_crtc->crtc_id = index;  in dce_v6_0_crtc_init()
2695 	adev->mode_info.crtcs[index] = amdgpu_crtc;  in dce_v6_0_crtc_init()
2697 	amdgpu_crtc->max_cursor_width = CURSOR_WIDTH;  in dce_v6_0_crtc_init()
2698 	amdgpu_crtc->max_cursor_height = CURSOR_HEIGHT;  in dce_v6_0_crtc_init()
2699 	adev_to_drm(adev)->mode_config.cursor_width = amdgpu_crtc->max_cursor_width;  in dce_v6_0_crtc_init()
2700 	adev_to_drm(adev)->mode_config.cursor_height = amdgpu_crtc->max_cursor_height;  in dce_v6_0_crtc_init()
2702 	amdgpu_crtc->crtc_offset = crtc_offsets[amdgpu_crtc->crtc_id];  in dce_v6_0_crtc_init()
2704 	amdgpu_crtc->pll_id = ATOM_PPLL_INVALID;  in dce_v6_0_crtc_init()
2705 	amdgpu_crtc->adjusted_clock = 0;  in dce_v6_0_crtc_init()
2706 	amdgpu_crtc->encoder = NULL;  in dce_v6_0_crtc_init()
2707 	amdgpu_crtc->connector = NULL;  in dce_v6_0_crtc_init()
2708 	drm_crtc_helper_add(&amdgpu_crtc->base, &dce_v6_0_crtc_helper_funcs);  in dce_v6_0_crtc_init()
2709 	drm_plane_helper_add(amdgpu_crtc->base.primary, &dce_v6_0_drm_primary_plane_helper_funcs);  in dce_v6_0_crtc_init()
3153 	struct amdgpu_crtc *amdgpu_crtc;  in dce_v6_0_pageflip_irq()  local
3157 	amdgpu_crtc = adev->mode_info.crtcs[crtc_id];  in dce_v6_0_pageflip_irq()
3170 	if (amdgpu_crtc == NULL)  in dce_v6_0_pageflip_irq()
3174 	works = amdgpu_crtc->pflip_works;  in dce_v6_0_pageflip_irq()
3175 	if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_SUBMITTED){  in dce_v6_0_pageflip_irq()
3178 						amdgpu_crtc->pflip_status,  in dce_v6_0_pageflip_irq()
3185 	amdgpu_crtc->pflip_status = AMDGPU_FLIP_NONE;  in dce_v6_0_pageflip_irq()
3186 	amdgpu_crtc->pflip_works = NULL;  in dce_v6_0_pageflip_irq()
3190 		drm_crtc_send_vblank_event(&amdgpu_crtc->base, works->event);  in dce_v6_0_pageflip_irq()
3194 	drm_crtc_vblank_put(&amdgpu_crtc->base);  in dce_v6_0_pageflip_irq()