Lines Matching refs:SDMA1_REGISTER_OFFSET
50 SDMA1_REGISTER_OFFSET
881 WREG32(mmSDMA0_CLK_CTRL + SDMA1_REGISTER_OFFSET, 0x00000100); in cik_enable_sdma_mgcg()
888 orig = data = RREG32(mmSDMA0_CLK_CTRL + SDMA1_REGISTER_OFFSET); in cik_enable_sdma_mgcg()
891 WREG32(mmSDMA0_CLK_CTRL + SDMA1_REGISTER_OFFSET, data); in cik_enable_sdma_mgcg()
906 orig = data = RREG32(mmSDMA0_POWER_CNTL + SDMA1_REGISTER_OFFSET); in cik_enable_sdma_mgls()
909 WREG32(mmSDMA0_POWER_CNTL + SDMA1_REGISTER_OFFSET, data); in cik_enable_sdma_mgls()
916 orig = data = RREG32(mmSDMA0_POWER_CNTL + SDMA1_REGISTER_OFFSET); in cik_enable_sdma_mgls()
919 WREG32(mmSDMA0_POWER_CNTL + SDMA1_REGISTER_OFFSET, data); in cik_enable_sdma_mgls()
1070 tmp = RREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET); in cik_sdma_soft_reset()
1072 WREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET, tmp); in cik_sdma_soft_reset()
1122 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET); in cik_sdma_set_trap_irq_state()
1124 WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl); in cik_sdma_set_trap_irq_state()
1127 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET); in cik_sdma_set_trap_irq_state()
1129 WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl); in cik_sdma_set_trap_irq_state()