Lines Matching refs:amdgpu_device

87 	int (*req_full_gpu)(struct amdgpu_device *adev, bool init);
88 	int (*rel_full_gpu)(struct amdgpu_device *adev, bool init);
89 	int (*req_init_data)(struct amdgpu_device *adev);
90 	int (*reset_gpu)(struct amdgpu_device *adev);
91 	void (*ready_to_reset)(struct amdgpu_device *adev);
92 	int (*wait_reset)(struct amdgpu_device *adev);
93 	void (*trans_msg)(struct amdgpu_device *adev, enum idh_request req,
95 	void (*ras_poison_handler)(struct amdgpu_device *adev,
97 	bool (*rcvd_ras_intr)(struct amdgpu_device *adev);
98 	int (*req_ras_err_count)(struct amdgpu_device *adev);
99 	int (*req_ras_cper_dump)(struct amdgpu_device *adev, u64 vf_rptr);
379 bool amdgpu_virt_mmio_blocked(struct amdgpu_device *adev);
380 void amdgpu_virt_init_setting(struct amdgpu_device *adev);
381 int amdgpu_virt_request_full_gpu(struct amdgpu_device *adev, bool init);
382 int amdgpu_virt_release_full_gpu(struct amdgpu_device *adev, bool init);
383 int amdgpu_virt_reset_gpu(struct amdgpu_device *adev);
384 void amdgpu_virt_request_init_data(struct amdgpu_device *adev);
385 void amdgpu_virt_ready_to_reset(struct amdgpu_device *adev);
386 int amdgpu_virt_wait_reset(struct amdgpu_device *adev);
387 int amdgpu_virt_alloc_mm_table(struct amdgpu_device *adev);
388 void amdgpu_virt_free_mm_table(struct amdgpu_device *adev);
389 bool amdgpu_virt_rcvd_ras_interrupt(struct amdgpu_device *adev);
390 void amdgpu_virt_release_ras_err_handler_data(struct amdgpu_device *adev);
391 void amdgpu_virt_init_data_exchange(struct amdgpu_device *adev);
392 void amdgpu_virt_exchange_data(struct amdgpu_device *adev);
393 void amdgpu_virt_fini_data_exchange(struct amdgpu_device *adev);
394 void amdgpu_virt_init(struct amdgpu_device *adev);
396 bool amdgpu_virt_can_access_debugfs(struct amdgpu_device *adev);
397 int amdgpu_virt_enable_access_debugfs(struct amdgpu_device *adev);
398 void amdgpu_virt_disable_access_debugfs(struct amdgpu_device *adev);
400 enum amdgpu_sriov_vf_mode amdgpu_virt_get_sriov_vf_mode(struct amdgpu_device *adev);
402 void amdgpu_virt_update_sriov_video_codec(struct amdgpu_device *adev,
405 void amdgpu_sriov_wreg(struct amdgpu_device *adev,
408 u32 amdgpu_sriov_rreg(struct amdgpu_device *adev,
410 bool amdgpu_virt_fw_load_skip_check(struct amdgpu_device *adev,
412 void amdgpu_virt_pre_reset(struct amdgpu_device *adev);
413 void amdgpu_virt_post_reset(struct amdgpu_device *adev);
414 bool amdgpu_sriov_xnack_support(struct amdgpu_device *adev);
415 bool amdgpu_virt_get_rlcg_reg_access_flag(struct amdgpu_device *adev,
418 u32 amdgpu_virt_rlcg_reg_rw(struct amdgpu_device *adev, u32 offset, u32 v, u32 flag, u32 xcc_id);
419 bool amdgpu_virt_get_ras_capability(struct amdgpu_device *adev);
420 int amdgpu_virt_req_ras_err_count(struct amdgpu_device *adev, enum amdgpu_ras_block block,
422 int amdgpu_virt_req_ras_cper_dump(struct amdgpu_device *adev, bool force_update);
423 int amdgpu_virt_ras_telemetry_post_reset(struct amdgpu_device *adev);
424 bool amdgpu_virt_ras_telemetry_block_en(struct amdgpu_device *adev,