87 	int (*req_full_gpu)(struct amdgpu_device *adev, bool init);
88 	int (*rel_full_gpu)(struct amdgpu_device *adev, bool init);
89 	int (*req_init_data)(struct amdgpu_device *adev);
90 	int (*reset_gpu)(struct amdgpu_device *adev);
91 	void (*ready_to_reset)(struct amdgpu_device *adev);
92 	int (*wait_reset)(struct amdgpu_device *adev);
93 	void (*trans_msg)(struct amdgpu_device *adev, enum idh_request req,
95 	void (*ras_poison_handler)(struct amdgpu_device *adev,
97 	bool (*rcvd_ras_intr)(struct amdgpu_device *adev);
98 	int (*req_ras_err_count)(struct amdgpu_device *adev);
99 	int (*req_ras_cper_dump)(struct amdgpu_device *adev, u64 vf_rptr);
302 #define amdgpu_sriov_enabled(adev) \  argument
303 ((adev)->virt.caps & AMDGPU_SRIOV_CAPS_ENABLE_IOV)
305 #define amdgpu_sriov_vf(adev) \  argument
306 ((adev)->virt.caps & AMDGPU_SRIOV_CAPS_IS_VF)
308 #define amdgpu_sriov_bios(adev) \  argument
309 ((adev)->virt.caps & AMDGPU_SRIOV_CAPS_SRIOV_VBIOS)
311 #define amdgpu_sriov_runtime(adev) \  argument
312 ((adev)->virt.caps & AMDGPU_SRIOV_CAPS_RUNTIME)
314 #define amdgpu_sriov_fullaccess(adev) \  argument
315 (amdgpu_sriov_vf((adev)) && !amdgpu_sriov_runtime((adev)))
317 #define amdgpu_sriov_reg_indirect_en(adev) \  argument
318 (amdgpu_sriov_vf((adev)) && \
319 	((adev)->virt.gim_feature & (AMDGIM_FEATURE_INDIRECT_REG_ACCESS)))
321 #define amdgpu_sriov_reg_indirect_ih(adev) \  argument
322 (amdgpu_sriov_vf((adev)) && \
323 	((adev)->virt.reg_access & (AMDGIM_FEATURE_IH_REG_PSP_EN)))
325 #define amdgpu_sriov_reg_indirect_mmhub(adev) \  argument
326 (amdgpu_sriov_vf((adev)) && \
327 	((adev)->virt.reg_access & (AMDGIM_FEATURE_MMHUB_REG_RLC_EN)))
329 #define amdgpu_sriov_reg_indirect_gc(adev) \  argument
330 (amdgpu_sriov_vf((adev)) && \
331 	((adev)->virt.reg_access & (AMDGIM_FEATURE_GC_REG_RLC_EN)))
333 #define amdgpu_sriov_rlcg_error_report_enabled(adev) \  argument
334         (amdgpu_sriov_reg_indirect_mmhub(adev) || amdgpu_sriov_reg_indirect_gc(adev))
336 #define amdgpu_passthrough(adev) \  argument
337 ((adev)->virt.caps & AMDGPU_PASSTHROUGH_MODE)
339 #define amdgpu_sriov_vf_mmio_access_protection(adev) \  argument
340 ((adev)->virt.caps & AMDGPU_VF_MMIO_ACCESS_PROTECT)
342 #define amdgpu_sriov_ras_caps_en(adev) \  argument
343 ((adev)->virt.gim_feature & AMDGIM_FEATURE_RAS_CAPS)
345 #define amdgpu_sriov_ras_telemetry_en(adev) \  argument
346 (((adev)->virt.gim_feature & AMDGIM_FEATURE_RAS_TELEMETRY) && (adev)->virt.fw_reserve.ras_telemetry)
348 #define amdgpu_sriov_ras_telemetry_block_en(adev, sriov_blk) \  argument
349 (amdgpu_sriov_ras_telemetry_en((adev)) && (adev)->virt.ras_telemetry_en_caps.all & BIT(sriov_blk))
351 #define amdgpu_sriov_ras_cper_en(adev) \  argument
352 ((adev)->virt.gim_feature & AMDGIM_FEATURE_RAS_CPER)
365 #define amdgpu_sriov_is_pp_one_vf(adev) \  argument
366 	((adev)->virt.gim_feature & AMDGIM_FEATURE_PP_ONE_VF)
367 #define amdgpu_sriov_multi_vf_mode(adev) \  argument
368 	(amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev))
369 #define amdgpu_sriov_is_debug(adev) \  argument
370 	((!amdgpu_in_reset(adev)) && adev->virt.tdr_debug)
371 #define amdgpu_sriov_is_normal(adev) \  argument
372 	((!amdgpu_in_reset(adev)) && (!adev->virt.tdr_debug))
373 #define amdgpu_sriov_is_av1_support(adev) \  argument
374 	((adev)->virt.gim_feature & AMDGIM_FEATURE_AV1_SUPPORT)
375 #define amdgpu_sriov_is_vcn_rb_decouple(adev) \  argument
376 	((adev)->virt.gim_feature & AMDGIM_FEATURE_VCN_RB_DECOUPLE)
377 #define amdgpu_sriov_is_mes_info_enable(adev) \  argument
378 	((adev)->virt.gim_feature & AMDGIM_FEATURE_MES_INFO_ENABLE)
379 bool amdgpu_virt_mmio_blocked(struct amdgpu_device *adev);
380 void amdgpu_virt_init_setting(struct amdgpu_device *adev);
381 int amdgpu_virt_request_full_gpu(struct amdgpu_device *adev, bool init);
382 int amdgpu_virt_release_full_gpu(struct amdgpu_device *adev, bool init);
383 int amdgpu_virt_reset_gpu(struct amdgpu_device *adev);
384 void amdgpu_virt_request_init_data(struct amdgpu_device *adev);
385 void amdgpu_virt_ready_to_reset(struct amdgpu_device *adev);
386 int amdgpu_virt_wait_reset(struct amdgpu_device *adev);
387 int amdgpu_virt_alloc_mm_table(struct amdgpu_device *adev);
388 void amdgpu_virt_free_mm_table(struct amdgpu_device *adev);
389 bool amdgpu_virt_rcvd_ras_interrupt(struct amdgpu_device *adev);
390 void amdgpu_virt_release_ras_err_handler_data(struct amdgpu_device *adev);
391 void amdgpu_virt_init_data_exchange(struct amdgpu_device *adev);
392 void amdgpu_virt_exchange_data(struct amdgpu_device *adev);
393 void amdgpu_virt_fini_data_exchange(struct amdgpu_device *adev);
394 void amdgpu_virt_init(struct amdgpu_device *adev);
396 bool amdgpu_virt_can_access_debugfs(struct amdgpu_device *adev);
397 int amdgpu_virt_enable_access_debugfs(struct amdgpu_device *adev);
398 void amdgpu_virt_disable_access_debugfs(struct amdgpu_device *adev);
400 enum amdgpu_sriov_vf_mode amdgpu_virt_get_sriov_vf_mode(struct amdgpu_device *adev);
402 void amdgpu_virt_update_sriov_video_codec(struct amdgpu_device *adev,
405 void amdgpu_sriov_wreg(struct amdgpu_device *adev,
408 u32 amdgpu_sriov_rreg(struct amdgpu_device *adev,
410 bool amdgpu_virt_fw_load_skip_check(struct amdgpu_device *adev,
412 void amdgpu_virt_pre_reset(struct amdgpu_device *adev);
413 void amdgpu_virt_post_reset(struct amdgpu_device *adev);
414 bool amdgpu_sriov_xnack_support(struct amdgpu_device *adev);
415 bool amdgpu_virt_get_rlcg_reg_access_flag(struct amdgpu_device *adev,
418 u32 amdgpu_virt_rlcg_reg_rw(struct amdgpu_device *adev, u32 offset, u32 v, u32 flag, u32 xcc_id);
419 bool amdgpu_virt_get_ras_capability(struct amdgpu_device *adev);
420 int amdgpu_virt_req_ras_err_count(struct amdgpu_device *adev, enum amdgpu_ras_block block,
422 int amdgpu_virt_req_ras_cper_dump(struct amdgpu_device *adev, bool force_update);
423 int amdgpu_virt_ras_telemetry_post_reset(struct amdgpu_device *adev);
424 bool amdgpu_virt_ras_telemetry_block_en(struct amdgpu_device *adev,