901 	struct mes_misc_op_input op_input;  in amdgpu_mes_rreg()  local
913 	op_input.op = MES_MISC_OP_READ_REG;  in amdgpu_mes_rreg()
914 	op_input.read_reg.reg_offset = reg;  in amdgpu_mes_rreg()
915 	op_input.read_reg.buffer_addr = read_val_gpu_addr;  in amdgpu_mes_rreg()
922 	r = adev->mes.funcs->misc_op(&adev->mes, &op_input);  in amdgpu_mes_rreg()
937 	struct mes_misc_op_input op_input;  in amdgpu_mes_wreg()  local
940 	op_input.op = MES_MISC_OP_WRITE_REG;  in amdgpu_mes_wreg()
941 	op_input.write_reg.reg_offset = reg;  in amdgpu_mes_wreg()
942 	op_input.write_reg.reg_value = val;  in amdgpu_mes_wreg()
950 	r = adev->mes.funcs->misc_op(&adev->mes, &op_input);  in amdgpu_mes_wreg()
962 	struct mes_misc_op_input op_input;  in amdgpu_mes_reg_write_reg_wait()  local
965 	op_input.op = MES_MISC_OP_WRM_REG_WR_WAIT;  in amdgpu_mes_reg_write_reg_wait()
966 	op_input.wrm_reg.reg0 = reg0;  in amdgpu_mes_reg_write_reg_wait()
967 	op_input.wrm_reg.reg1 = reg1;  in amdgpu_mes_reg_write_reg_wait()
968 	op_input.wrm_reg.ref = ref;  in amdgpu_mes_reg_write_reg_wait()
969 	op_input.wrm_reg.mask = mask;  in amdgpu_mes_reg_write_reg_wait()
977 	r = adev->mes.funcs->misc_op(&adev->mes, &op_input);  in amdgpu_mes_reg_write_reg_wait()
988 	struct mes_misc_op_input op_input;  in amdgpu_mes_reg_wait()  local
991 	op_input.op = MES_MISC_OP_WRM_REG_WAIT;  in amdgpu_mes_reg_wait()
992 	op_input.wrm_reg.reg0 = reg;  in amdgpu_mes_reg_wait()
993 	op_input.wrm_reg.ref = val;  in amdgpu_mes_reg_wait()
994 	op_input.wrm_reg.mask = mask;  in amdgpu_mes_reg_wait()
1002 	r = adev->mes.funcs->misc_op(&adev->mes, &op_input);  in amdgpu_mes_reg_wait()
1017 	struct mes_misc_op_input op_input = {0};  in amdgpu_mes_set_shader_debugger()  local
1025 	op_input.op = MES_MISC_OP_SET_SHADER_DEBUGGER;  in amdgpu_mes_set_shader_debugger()
1026 	op_input.set_shader_debugger.process_context_addr = process_context_addr;  in amdgpu_mes_set_shader_debugger()
1027 	op_input.set_shader_debugger.flags.u32all = flags;  in amdgpu_mes_set_shader_debugger()
1030 	if (op_input.set_shader_debugger.flags.process_ctx_flush)  in amdgpu_mes_set_shader_debugger()
1033 	op_input.set_shader_debugger.spi_gdbg_per_vmid_cntl = spi_gdbg_per_vmid_cntl;  in amdgpu_mes_set_shader_debugger()
1034 	memcpy(op_input.set_shader_debugger.tcp_watch_cntl, tcp_watch_cntl,  in amdgpu_mes_set_shader_debugger()
1035 			sizeof(op_input.set_shader_debugger.tcp_watch_cntl));  in amdgpu_mes_set_shader_debugger()
1039 		op_input.set_shader_debugger.trap_en = trap_en;  in amdgpu_mes_set_shader_debugger()
1043 	r = adev->mes.funcs->misc_op(&adev->mes, &op_input);  in amdgpu_mes_set_shader_debugger()
1055 	struct mes_misc_op_input op_input = {0};  in amdgpu_mes_flush_shader_debugger()  local
1063 	op_input.op = MES_MISC_OP_SET_SHADER_DEBUGGER;  in amdgpu_mes_flush_shader_debugger()
1064 	op_input.set_shader_debugger.process_context_addr = process_context_addr;  in amdgpu_mes_flush_shader_debugger()
1065 	op_input.set_shader_debugger.flags.process_ctx_flush = true;  in amdgpu_mes_flush_shader_debugger()
1069 	r = adev->mes.funcs->misc_op(&adev->mes, &op_input);  in amdgpu_mes_flush_shader_debugger()
1681 	struct mes_misc_op_input op_input = {0};  in amdgpu_mes_set_enforce_isolation()  local
1684 	op_input.op = MES_MISC_OP_CHANGE_CONFIG;  in amdgpu_mes_set_enforce_isolation()
1685 	op_input.change_config.option.limit_single_process = enable ? 1 : 0;  in amdgpu_mes_set_enforce_isolation()
1693 	r = adev->mes.funcs->misc_op(&adev->mes, &op_input);  in amdgpu_mes_set_enforce_isolation()