847 		struct drm_amdgpu_info_device *dev_info;  in amdgpu_info_ioctl()  local
851 		dev_info = kzalloc(sizeof(*dev_info), GFP_KERNEL);  in amdgpu_info_ioctl()
852 		if (!dev_info)  in amdgpu_info_ioctl()
855 		dev_info->device_id = adev->pdev->device;  in amdgpu_info_ioctl()
856 		dev_info->chip_rev = adev->rev_id;  in amdgpu_info_ioctl()
857 		dev_info->external_rev = adev->external_rev_id;  in amdgpu_info_ioctl()
858 		dev_info->pci_rev = adev->pdev->revision;  in amdgpu_info_ioctl()
859 		dev_info->family = adev->family;  in amdgpu_info_ioctl()
860 		dev_info->num_shader_engines = adev->gfx.config.max_shader_engines;  in amdgpu_info_ioctl()
861 		dev_info->num_shader_arrays_per_engine = adev->gfx.config.max_sh_per_se;  in amdgpu_info_ioctl()
863 		dev_info->gpu_counter_freq = amdgpu_asic_get_xclk(adev) * 10;  in amdgpu_info_ioctl()
865 			dev_info->max_engine_clock = amdgpu_dpm_get_sclk(adev, false) * 10;  in amdgpu_info_ioctl()
866 			dev_info->max_memory_clock = amdgpu_dpm_get_mclk(adev, false) * 10;  in amdgpu_info_ioctl()
867 			dev_info->min_engine_clock = amdgpu_dpm_get_sclk(adev, true) * 10;  in amdgpu_info_ioctl()
868 			dev_info->min_memory_clock = amdgpu_dpm_get_mclk(adev, true) * 10;  in amdgpu_info_ioctl()
870 			dev_info->max_engine_clock =  in amdgpu_info_ioctl()
871 				dev_info->min_engine_clock =  in amdgpu_info_ioctl()
873 			dev_info->max_memory_clock =  in amdgpu_info_ioctl()
874 				dev_info->min_memory_clock =  in amdgpu_info_ioctl()
877 		dev_info->enabled_rb_pipes_mask = adev->gfx.config.backend_enable_mask;  in amdgpu_info_ioctl()
878 		dev_info->num_rb_pipes = adev->gfx.config.max_backends_per_se *  in amdgpu_info_ioctl()
880 		dev_info->num_hw_gfx_contexts = adev->gfx.config.max_hw_contexts;  in amdgpu_info_ioctl()
881 		dev_info->ids_flags = 0;  in amdgpu_info_ioctl()
883 			dev_info->ids_flags |= AMDGPU_IDS_FLAGS_FUSION;  in amdgpu_info_ioctl()
885 			dev_info->ids_flags |= AMDGPU_IDS_FLAGS_PREEMPTION;  in amdgpu_info_ioctl()
887 			dev_info->ids_flags |= AMDGPU_IDS_FLAGS_TMZ;  in amdgpu_info_ioctl()
889 			dev_info->ids_flags |= AMDGPU_IDS_FLAGS_CONFORMANT_TRUNC_COORD;  in amdgpu_info_ioctl()
892 			dev_info->ids_flags |= (AMDGPU_IDS_FLAGS_MODE_PT <<  in amdgpu_info_ioctl()
896 			dev_info->ids_flags |= (AMDGPU_IDS_FLAGS_MODE_VF <<  in amdgpu_info_ioctl()
908 		dev_info->virtual_address_offset = AMDGPU_VA_RESERVED_BOTTOM;  in amdgpu_info_ioctl()
909 		dev_info->virtual_address_max =  in amdgpu_info_ioctl()
913 			dev_info->high_va_offset = AMDGPU_GMC_HOLE_END;  in amdgpu_info_ioctl()
914 			dev_info->high_va_max = AMDGPU_GMC_HOLE_END | vm_size;  in amdgpu_info_ioctl()
916 		dev_info->virtual_address_alignment = max_t(u32, PAGE_SIZE, AMDGPU_GPU_PAGE_SIZE);  in amdgpu_info_ioctl()
917 		dev_info->pte_fragment_size = (1 << adev->vm_manager.fragment_size) * AMDGPU_GPU_PAGE_SIZE;  in amdgpu_info_ioctl()
918 		dev_info->gart_page_size = max_t(u32, PAGE_SIZE, AMDGPU_GPU_PAGE_SIZE);  in amdgpu_info_ioctl()
919 		dev_info->cu_active_number = adev->gfx.cu_info.number;  in amdgpu_info_ioctl()
920 		dev_info->cu_ao_mask = adev->gfx.cu_info.ao_cu_mask;  in amdgpu_info_ioctl()
921 		dev_info->ce_ram_size = adev->gfx.ce_ram_size;  in amdgpu_info_ioctl()
922 		memcpy(&dev_info->cu_ao_bitmap[0], &adev->gfx.cu_info.ao_cu_bitmap[0],  in amdgpu_info_ioctl()
924 		memcpy(&dev_info->cu_bitmap[0], &adev->gfx.cu_info.bitmap[0],  in amdgpu_info_ioctl()
925 		       sizeof(dev_info->cu_bitmap));  in amdgpu_info_ioctl()
926 		dev_info->vram_type = adev->gmc.vram_type;  in amdgpu_info_ioctl()
927 		dev_info->vram_bit_width = adev->gmc.vram_width;  in amdgpu_info_ioctl()
928 		dev_info->vce_harvest_config = adev->vce.harvest_config;  in amdgpu_info_ioctl()
929 		dev_info->gc_double_offchip_lds_buf =  in amdgpu_info_ioctl()
931 		dev_info->wave_front_size = adev->gfx.cu_info.wave_front_size;  in amdgpu_info_ioctl()
932 		dev_info->num_shader_visible_vgprs = adev->gfx.config.max_gprs;  in amdgpu_info_ioctl()
933 		dev_info->num_cu_per_sh = adev->gfx.config.max_cu_per_sh;  in amdgpu_info_ioctl()
934 		dev_info->num_tcc_blocks = adev->gfx.config.max_texture_channel_caches;  in amdgpu_info_ioctl()
935 		dev_info->gs_vgt_table_depth = adev->gfx.config.gs_vgt_table_depth;  in amdgpu_info_ioctl()
936 		dev_info->gs_prim_buffer_depth = adev->gfx.config.gs_prim_buffer_depth;  in amdgpu_info_ioctl()
937 		dev_info->max_gs_waves_per_vgt = adev->gfx.config.max_gs_threads;  in amdgpu_info_ioctl()
940 			dev_info->pa_sc_tile_steering_override =  in amdgpu_info_ioctl()
943 		dev_info->tcc_disabled_mask = adev->gfx.config.tcc_disabled_mask;  in amdgpu_info_ioctl()
950 		dev_info->pcie_gen = fls(pcie_gen_mask);  in amdgpu_info_ioctl()
951 		dev_info->pcie_num_lanes =  in amdgpu_info_ioctl()
959 		dev_info->tcp_cache_size = adev->gfx.config.gc_tcp_l1_size;  in amdgpu_info_ioctl()
960 		dev_info->num_sqc_per_wgp = adev->gfx.config.gc_num_sqc_per_wgp;  in amdgpu_info_ioctl()
961 		dev_info->sqc_data_cache_size = adev->gfx.config.gc_l1_data_cache_size_per_sqc;  in amdgpu_info_ioctl()
962 		dev_info->sqc_inst_cache_size = adev->gfx.config.gc_l1_instruction_cache_size_per_sqc;  in amdgpu_info_ioctl()
963 		dev_info->gl1c_cache_size = adev->gfx.config.gc_gl1c_size_per_instance *  in amdgpu_info_ioctl()
965 		dev_info->gl2c_cache_size = adev->gfx.config.gc_gl2c_per_gpu;  in amdgpu_info_ioctl()
966 		dev_info->mall_size = adev->gmc.mall_size;  in amdgpu_info_ioctl()
974 				dev_info->shadow_size = shadow_info.shadow_size;  in amdgpu_info_ioctl()
975 				dev_info->shadow_alignment = shadow_info.shadow_alignment;  in amdgpu_info_ioctl()
976 				dev_info->csa_size = shadow_info.csa_size;  in amdgpu_info_ioctl()
977 				dev_info->csa_alignment = shadow_info.csa_alignment;  in amdgpu_info_ioctl()
981 		ret = copy_to_user(out, dev_info,  in amdgpu_info_ioctl()
982 				   min((size_t)size, sizeof(*dev_info))) ? -EFAULT : 0;  in amdgpu_info_ioctl()
983 		kfree(dev_info);  in amdgpu_info_ioctl()