884 	uint32_t *config, no_regs = 0;  in amdgpu_debugfs_gca_config_read()  local
894 	config[no_regs++] = 5;  in amdgpu_debugfs_gca_config_read()
895 	config[no_regs++] = adev->gfx.config.max_shader_engines;  in amdgpu_debugfs_gca_config_read()
896 	config[no_regs++] = adev->gfx.config.max_tile_pipes;  in amdgpu_debugfs_gca_config_read()
897 	config[no_regs++] = adev->gfx.config.max_cu_per_sh;  in amdgpu_debugfs_gca_config_read()
898 	config[no_regs++] = adev->gfx.config.max_sh_per_se;  in amdgpu_debugfs_gca_config_read()
899 	config[no_regs++] = adev->gfx.config.max_backends_per_se;  in amdgpu_debugfs_gca_config_read()
900 	config[no_regs++] = adev->gfx.config.max_texture_channel_caches;  in amdgpu_debugfs_gca_config_read()
901 	config[no_regs++] = adev->gfx.config.max_gprs;  in amdgpu_debugfs_gca_config_read()
902 	config[no_regs++] = adev->gfx.config.max_gs_threads;  in amdgpu_debugfs_gca_config_read()
903 	config[no_regs++] = adev->gfx.config.max_hw_contexts;  in amdgpu_debugfs_gca_config_read()
904 	config[no_regs++] = adev->gfx.config.sc_prim_fifo_size_frontend;  in amdgpu_debugfs_gca_config_read()
905 	config[no_regs++] = adev->gfx.config.sc_prim_fifo_size_backend;  in amdgpu_debugfs_gca_config_read()
906 	config[no_regs++] = adev->gfx.config.sc_hiz_tile_fifo_size;  in amdgpu_debugfs_gca_config_read()
907 	config[no_regs++] = adev->gfx.config.sc_earlyz_tile_fifo_size;  in amdgpu_debugfs_gca_config_read()
908 	config[no_regs++] = adev->gfx.config.num_tile_pipes;  in amdgpu_debugfs_gca_config_read()
909 	config[no_regs++] = adev->gfx.config.backend_enable_mask;  in amdgpu_debugfs_gca_config_read()
910 	config[no_regs++] = adev->gfx.config.mem_max_burst_length_bytes;  in amdgpu_debugfs_gca_config_read()
911 	config[no_regs++] = adev->gfx.config.mem_row_size_in_kb;  in amdgpu_debugfs_gca_config_read()
912 	config[no_regs++] = adev->gfx.config.shader_engine_tile_size;  in amdgpu_debugfs_gca_config_read()
913 	config[no_regs++] = adev->gfx.config.num_gpus;  in amdgpu_debugfs_gca_config_read()
914 	config[no_regs++] = adev->gfx.config.multi_gpu_tile_size;  in amdgpu_debugfs_gca_config_read()
915 	config[no_regs++] = adev->gfx.config.mc_arb_ramcfg;  in amdgpu_debugfs_gca_config_read()
916 	config[no_regs++] = adev->gfx.config.gb_addr_config;  in amdgpu_debugfs_gca_config_read()
917 	config[no_regs++] = adev->gfx.config.num_rbs;  in amdgpu_debugfs_gca_config_read()
920 	config[no_regs++] = adev->rev_id;  in amdgpu_debugfs_gca_config_read()
921 	config[no_regs++] = adev->pg_flags;  in amdgpu_debugfs_gca_config_read()
922 	config[no_regs++] = lower_32_bits(adev->cg_flags);  in amdgpu_debugfs_gca_config_read()
925 	config[no_regs++] = adev->family;  in amdgpu_debugfs_gca_config_read()
926 	config[no_regs++] = adev->external_rev_id;  in amdgpu_debugfs_gca_config_read()
929 	config[no_regs++] = adev->pdev->device;  in amdgpu_debugfs_gca_config_read()
930 	config[no_regs++] = adev->pdev->revision;  in amdgpu_debugfs_gca_config_read()
931 	config[no_regs++] = adev->pdev->subsystem_device;  in amdgpu_debugfs_gca_config_read()
932 	config[no_regs++] = adev->pdev->subsystem_vendor;  in amdgpu_debugfs_gca_config_read()
935 	config[no_regs++] = adev->flags & AMD_IS_APU ? 1 : 0;  in amdgpu_debugfs_gca_config_read()
938 	config[no_regs++] = 0;  in amdgpu_debugfs_gca_config_read()
939 	config[no_regs++] = upper_32_bits(adev->cg_flags);  in amdgpu_debugfs_gca_config_read()
941 	while (size && (*pos < no_regs * 4)) {  in amdgpu_debugfs_gca_config_read()