157 static inline void dwapb_write(struct dwapb_gpio *gpio, unsigned int offset,  in dwapb_write()  function
199 	dwapb_write(gpio, GPIO_INT_POLARITY, pol);  in dwapb_toggle_trigger()
245 	dwapb_write(gpio, GPIO_PORTA_EOI, val);  in dwapb_irq_ack()
259 	dwapb_write(gpio, GPIO_INTMASK, val);  in dwapb_irq_mask()
277 	dwapb_write(gpio, GPIO_INTMASK, val);  in dwapb_irq_unmask()
291 	dwapb_write(gpio, GPIO_INTEN, val);  in dwapb_irq_enable()
293 	dwapb_write(gpio, GPIO_INTMASK, val);  in dwapb_irq_enable()
307 	dwapb_write(gpio, GPIO_INTMASK, val);  in dwapb_irq_disable()
309 	dwapb_write(gpio, GPIO_INTEN, val);  in dwapb_irq_disable()
352 	dwapb_write(gpio, GPIO_INTTYPE_LEVEL, level);  in dwapb_irq_set_type()
354 		dwapb_write(gpio, GPIO_INT_POLARITY, polarity);  in dwapb_irq_set_type()
407 	dwapb_write(gpio, GPIO_PORTA_DEBOUNCE, val_deb);  in dwapb_gpio_set_debounce()
781 			dwapb_write(gpio, GPIO_INTMASK, ~ctx->wake_en);  in dwapb_gpio_suspend()
811 		dwapb_write(gpio, offset, ctx->data);  in dwapb_gpio_resume()
814 		dwapb_write(gpio, offset, ctx->dir);  in dwapb_gpio_resume()
817 		dwapb_write(gpio, offset, ctx->ext);  in dwapb_gpio_resume()
821 			dwapb_write(gpio, GPIO_INTTYPE_LEVEL, ctx->int_type);  in dwapb_gpio_resume()
822 			dwapb_write(gpio, GPIO_INT_POLARITY, ctx->int_pol);  in dwapb_gpio_resume()
823 			dwapb_write(gpio, GPIO_PORTA_DEBOUNCE, ctx->int_deb);  in dwapb_gpio_resume()
824 			dwapb_write(gpio, GPIO_INTEN, ctx->int_en);  in dwapb_gpio_resume()
825 			dwapb_write(gpio, GPIO_INTMASK, ctx->int_mask);  in dwapb_gpio_resume()
828 			dwapb_write(gpio, GPIO_PORTA_EOI, 0xffffffff);  in dwapb_gpio_resume()