388 				   struct device_node *node)  in load_one_timing_from_dt()  argument
393 	err = of_property_read_u32(node, "clock-frequency", &tmp);  in load_one_timing_from_dt()
395 		pr_err("timing %pOF: failed to read rate\n", node);  in load_one_timing_from_dt()
401 	err = of_property_read_u32(node, "nvidia,parent-clock-frequency", &tmp);  in load_one_timing_from_dt()
403 		pr_err("timing %pOF: failed to read parent rate\n", node);  in load_one_timing_from_dt()
409 	timing->parent = of_clk_get_by_name(node, "emc-parent");  in load_one_timing_from_dt()
411 		pr_err("timing %pOF: failed to get parent clock\n", node);  in load_one_timing_from_dt()
420 		       node, __clk_get_name(timing->parent));  in load_one_timing_from_dt()
443 				struct device_node *node,  in load_timings_from_dt()  argument
448 	int child_count = of_get_child_count(node);  in load_timings_from_dt()
461 	for_each_child_of_node(node, child) {  in load_timings_from_dt()
492 	struct device_node *node;  in tegra124_clk_register_emc()  local
506 	for_each_child_of_node(np, node) {  in tegra124_clk_register_emc()
507 		err = of_property_read_u32(node, "nvidia,ram-code",  in tegra124_clk_register_emc()
516 		err = load_timings_from_dt(tegra, node, node_ram_code);  in tegra124_clk_register_emc()
518 			of_node_put(node);  in tegra124_clk_register_emc()