556 static struct clk * __init sunxi_factors_clk_setup(struct device_node *node,  in sunxi_factors_clk_setup()  argument
561 	reg = of_iomap(node, 0);  in sunxi_factors_clk_setup()
564 		       node);  in sunxi_factors_clk_setup()
568 	return sunxi_factors_register(node, data, &clk_lock, reg);  in sunxi_factors_clk_setup()
571 static void __init sun4i_pll1_clk_setup(struct device_node *node)  in sun4i_pll1_clk_setup()  argument
573 	sunxi_factors_clk_setup(node, &sun4i_pll1_data);  in sun4i_pll1_clk_setup()
578 static void __init sun6i_pll1_clk_setup(struct device_node *node)  in sun6i_pll1_clk_setup()  argument
580 	sunxi_factors_clk_setup(node, &sun6i_a31_pll1_data);  in sun6i_pll1_clk_setup()
585 static void __init sun8i_pll1_clk_setup(struct device_node *node)  in sun8i_pll1_clk_setup()  argument
587 	sunxi_factors_clk_setup(node, &sun8i_a23_pll1_data);  in sun8i_pll1_clk_setup()
592 static void __init sun7i_pll4_clk_setup(struct device_node *node)  in sun7i_pll4_clk_setup()  argument
594 	sunxi_factors_clk_setup(node, &sun7i_a20_pll4_data);  in sun7i_pll4_clk_setup()
599 static void __init sun5i_ahb_clk_setup(struct device_node *node)  in sun5i_ahb_clk_setup()  argument
601 	sunxi_factors_clk_setup(node, &sun5i_a13_ahb_data);  in sun5i_ahb_clk_setup()
606 static void __init sun6i_ahb1_clk_setup(struct device_node *node)  in sun6i_ahb1_clk_setup()  argument
608 	sunxi_factors_clk_setup(node, &sun6i_ahb1_data);  in sun6i_ahb1_clk_setup()
613 static void __init sun4i_apb1_clk_setup(struct device_node *node)  in sun4i_apb1_clk_setup()  argument
615 	sunxi_factors_clk_setup(node, &sun4i_apb1_data);  in sun4i_apb1_clk_setup()
620 static void __init sun7i_out_clk_setup(struct device_node *node)  in sun7i_out_clk_setup()  argument
622 	sunxi_factors_clk_setup(node, &sun7i_a20_out_data);  in sun7i_out_clk_setup()
650 static struct clk * __init sunxi_mux_clk_setup(struct device_node *node,  in sunxi_mux_clk_setup()  argument
655 	const char *clk_name = node->name;  in sunxi_mux_clk_setup()
660 	reg = of_iomap(node, 0);  in sunxi_mux_clk_setup()
662 		pr_err("Could not map registers for mux-clk: %pOF\n", node);  in sunxi_mux_clk_setup()
666 	i = of_clk_parent_fill(node, parents, SUNXI_MAX_PARENTS);  in sunxi_mux_clk_setup()
667 	if (of_property_read_string(node, "clock-output-names", &clk_name)) {  in sunxi_mux_clk_setup()
669 		       __func__, node);  in sunxi_mux_clk_setup()
684 	if (of_clk_add_provider(node, of_clk_src_simple_get, clk)) {  in sunxi_mux_clk_setup()
697 static void __init sun4i_cpu_clk_setup(struct device_node *node)  in sun4i_cpu_clk_setup()  argument
700 	sunxi_mux_clk_setup(node, &sun4i_cpu_mux_data, CLK_IS_CRITICAL);  in sun4i_cpu_clk_setup()
705 static void __init sun6i_ahb1_mux_clk_setup(struct device_node *node)  in sun6i_ahb1_mux_clk_setup()  argument
707 	sunxi_mux_clk_setup(node, &sun6i_a31_ahb1_mux_data, 0);  in sun6i_ahb1_mux_clk_setup()
712 static void __init sun8i_ahb2_clk_setup(struct device_node *node)  in sun8i_ahb2_clk_setup()  argument
714 	sunxi_mux_clk_setup(node, &sun8i_h3_ahb2_mux_data, 0);  in sun8i_ahb2_clk_setup()
775 static void __init sunxi_divider_clk_setup(struct device_node *node,  in sunxi_divider_clk_setup()  argument
779 	const char *clk_name = node->name;  in sunxi_divider_clk_setup()
783 	reg = of_iomap(node, 0);  in sunxi_divider_clk_setup()
785 		pr_err("Could not map registers for mux-clk: %pOF\n", node);  in sunxi_divider_clk_setup()
789 	clk_parent = of_clk_get_parent_name(node, 0);  in sunxi_divider_clk_setup()
791 	if (of_property_read_string(node, "clock-output-names", &clk_name)) {  in sunxi_divider_clk_setup()
793 		       __func__, node);  in sunxi_divider_clk_setup()
807 	if (of_clk_add_provider(node, of_clk_src_simple_get, clk)) {  in sunxi_divider_clk_setup()
814 		of_clk_del_provider(node);  in sunxi_divider_clk_setup()
826 static void __init sun4i_ahb_clk_setup(struct device_node *node)  in sun4i_ahb_clk_setup()  argument
828 	sunxi_divider_clk_setup(node, &sun4i_ahb_data);  in sun4i_ahb_clk_setup()
833 static void __init sun4i_apb0_clk_setup(struct device_node *node)  in sun4i_apb0_clk_setup()  argument
835 	sunxi_divider_clk_setup(node, &sun4i_apb0_data);  in sun4i_apb0_clk_setup()
840 static void __init sun4i_axi_clk_setup(struct device_node *node)  in sun4i_axi_clk_setup()  argument
842 	sunxi_divider_clk_setup(node, &sun4i_axi_data);  in sun4i_axi_clk_setup()
847 static void __init sun8i_axi_clk_setup(struct device_node *node)  in sun8i_axi_clk_setup()  argument
849 	sunxi_divider_clk_setup(node, &sun8i_a23_axi_data);  in sun8i_axi_clk_setup()
932 static struct clk ** __init sunxi_divs_clk_setup(struct device_node *node,  in sunxi_divs_clk_setup()  argument
957 			of_property_read_string_index(node, "clock-output-names",  in sunxi_divs_clk_setup()
966 		of_property_read_string_index(node, "clock-output-names",  in sunxi_divs_clk_setup()
981 	pclk = sunxi_factors_clk_setup(node, &factors);  in sunxi_divs_clk_setup()
988 	reg = of_iomap(node, 0);  in sunxi_divs_clk_setup()
990 		pr_err("Could not map registers for divs-clk: %pOF\n", node);  in sunxi_divs_clk_setup()
1009 		if (of_property_read_string_index(node, "clock-output-names",  in sunxi_divs_clk_setup()
1081 	if (of_clk_add_provider(node, of_clk_src_onecell_get, clk_data)) {  in sunxi_divs_clk_setup()
1099 static void __init sun4i_pll5_clk_setup(struct device_node *node)  in sun4i_pll5_clk_setup()  argument
1101 	sunxi_divs_clk_setup(node, &pll5_divs_data);  in sun4i_pll5_clk_setup()
1106 static void __init sun4i_pll6_clk_setup(struct device_node *node)  in sun4i_pll6_clk_setup()  argument
1108 	sunxi_divs_clk_setup(node, &pll6_divs_data);  in sun4i_pll6_clk_setup()
1113 static void __init sun6i_pll6_clk_setup(struct device_node *node)  in sun6i_pll6_clk_setup()  argument
1115 	sunxi_divs_clk_setup(node, &sun6i_a31_pll6_divs_data);  in sun6i_pll6_clk_setup()
1151 static void __init sun6i_display_setup(struct device_node *node)  in sun6i_display_setup()  argument
1153 	sunxi_factors_clk_setup(node, &sun6i_display_data);  in sun6i_display_setup()