Lines Matching refs:bitmsk
137 u8 bitmsk; member
227 return !!(src & pfd_mux->bitmsk); in vc3_pfd_mux_get_parent()
235 return regmap_update_bits(vc3->regmap, pfd_mux->offs, pfd_mux->bitmsk, in vc3_pfd_mux_set_parent()
236 index ? pfd_mux->bitmsk : 0); in vc3_pfd_mux_set_parent()
456 return !!(src & div_mux->bitmsk); in vc3_div_mux_get_parent()
464 return regmap_update_bits(vc3->regmap, div_mux->offs, div_mux->bitmsk, in vc3_div_mux_set_parent()
465 index ? div_mux->bitmsk : 0); in vc3_div_mux_set_parent()
568 return !!(val & clk_mux->bitmsk); in vc3_clk_mux_get_parent()
576 return regmap_update_bits(vc3->regmap, clk_mux->offs, clk_mux->bitmsk, in vc3_clk_mux_set_parent()
577 index ? clk_mux->bitmsk : 0); in vc3_clk_mux_set_parent()
604 .bitmsk = BIT(VC3_PLL_OP_CTRL_PLL2_REFIN_SEL)
617 .bitmsk = BIT(VC3_GENERAL_CTR_PLL3_REFIN_SEL)
761 .bitmsk = VC3_GENERAL_CTR_DIV1_SRC_SEL
774 .bitmsk = VC3_PLL3_CHARGE_PUMP_CTRL_OUTDIV3_SRC_SEL
787 .bitmsk = VC3_OUTPUT_CTR_DIV4_SRC_SEL
896 .bitmsk = VC3_SE1_DIV4_CTRL_SE1_CLK_SEL
927 .bitmsk = VC3_SE3_DIFF1_CTRL_REG_SE3_CLK_SEL
943 .bitmsk = VC3_DIFF1_CTRL_REG_DIFF1_CLK_SEL
959 .bitmsk = VC3_DIFF2_CTRL_REG_DIFF2_CLK_SEL
1080 clk_data->bitmsk = data->se2_clk_sel_msk; in vc3_probe()