Lines Matching refs:orr
39 orr x0, x0, #HCR_E2H
61 orr x0, x0, #HCRX_EL2_GCSEn
117 orr x2, x2, x0 // If we don't have VHE, then
130 orr x2, x2, x0 // allow the EL1&0 translation
158 orr x0, x0, #ICC_SRE_EL2_SRE // Set ICC_SRE_EL2.SRE==1
159 orr x0, x0, #ICC_SRE_EL2_ENABLE // Set ICC_SRE_EL2.Enable==1
204 orr x0, x0, #(1 << 62)
216 orr x0, x0, #HFGxTR_EL2_nSMPRI_EL1_MASK
217 orr x0, x0, #HFGxTR_EL2_nTPIDR2_EL0_MASK
225 orr x0, x0, #HFGxTR_EL2_nPIR_EL1
226 orr x0, x0, #HFGxTR_EL2_nPIRE0_EL1
234 orr x0, x0, #HFGxTR_EL2_nPOR_EL0
243 orr x0, x0, #HFGxTR_EL2_nGCS_EL1_MASK
244 orr x0, x0, #HFGxTR_EL2_nGCS_EL0_MASK
274 orr x0, x0, #HDFGRTR2_EL2_nPMICNTR_EL0
275 orr x0, x0, #HDFGRTR2_EL2_nPMICFILTR_EL0
276 orr x0, x0, #HDFGRTR2_EL2_nPMUACR_EL1
381 orr x0, x0, #CPACR_EL1_ZEN
402 orr x0, x0, #CPACR_EL1_SMEN
414 orr x1, x1, #SCTLR_ELx_ENTP2 // Disable TPIDR2 traps
425 orr x0, x0, SMCR_ELx_FA64_MASK
432 orr x0, x0, SMCR_ELx_EZT0_MASK
435 orr x0, x0, #SMCR_ELx_LEN_MASK // Enable full SME vector