Lines Matching refs:workaround
461 The workaround forces KVM to explicitly set VTCR_EL2.HA to 0,
484 The workaround promotes data cache clean instructions to
486 Please note that this does not necessarily enable the workaround,
506 The workaround promotes data cache clean instructions to
508 Please note that this does not necessarily enable the workaround,
529 The workaround promotes data cache clean instructions to
532 workaround, as it depends on the alternative framework, which will
551 The workaround promotes data cache clean instructions to
553 Please note that this does not necessarily enable the workaround,
569 The workaround is to promote device loads to use Load-Acquire
571 Please note that this does not necessarily enable the workaround,
589 The workaround is to verify that the Stage 1 translation
591 Please note that this does not necessarily enable the workaround,
603 workaround erratum 1742098 on Cortex-A57 and Cortex-A72.
626 The workaround is to write the contextidr_el1 register on exception
628 Please note that this does not necessarily enable the workaround,
652 This option adds a workaround for ARM Cortex-A55 Erratum 1024718.
656 without a break-before-make. The workaround is to disable the usage
667 This option adds a workaround for ARM Cortex-A76/Neoverse-N1
684 This option adds a workaround for ARM Cortex-A76 erratum 1165522.
710 This option adds a workaround for ARM Cortex-A55 erratum 1530923.
725 This option adds a workaround for ARM Cortex-A55 erratum #2441007.
741 This option adds a workaround for ARM Cortex-A76 erratum 1286807.
750 workaround repeats the TLBI+DSB operation.
758 This option adds a workaround for Arm Cortex-A76 erratum 1463225.
773 bool "Neoverse-N1: workaround mis-ordering of instruction fetches (rare)"
775 This option adds a workaround for ARM Neoverse-N1 erratum
779 modified by another CPU. The workaround depends on a firmware
788 …bool "Cortex-A77: 1508412: workaround deadlock on sequence of NC/Device load and store exclusive o…
791 This option adds a workaround for Arm Cortex-A77 erratum 1508412.
795 non-cacheable memory attributes. The workaround depends on a firmware
798 KVM guests must also have the workaround implemented or they can
814 This options adds the workaround for ARM Cortex-A510 erratum ARM64_ERRATUM_2051678.
816 hardware update of the page table's dirty bit. The workaround
822 bool "Cortex-A510: 2077057: workaround software-step corrupting SPSR_EL2"
825 This option adds the workaround for ARM Cortex-A510 erratum 2077057.
842 This option adds the workaround for ARM Cortex-A510 erratum 2658417.
852 bool "Cortex-A710/X2: 2119858: workaround TRBE overwriting trace data in FILL mode"
857 This option adds the workaround for ARM Cortex-A710/X2 erratum 2119858.
870 bool "Neoverse-N2: 2139208: workaround TRBE overwriting trace data in FILL mode"
875 This option adds the workaround for ARM Neoverse-N2 erratum 2139208.
891 bool "Cortex-A710: 2054223: workaround TSB instruction failing to flush trace"
895 Enable workaround for ARM Cortex-A710 erratum 2054223
906 bool "Neoverse-N2: 2067961: workaround TSB instruction failing to flush trace"
910 Enable workaround for ARM Neoverse-N2 erratum 2067961
924 bool "Neoverse-N2: 2253138: workaround TRBE writing to address out-of-range"
929 This option adds the workaround for ARM Neoverse-N2 erratum 2253138.
942 bool "Cortex-A710/X2: 2224489: workaround TRBE writing to address out-of-range"
947 This option adds the workaround for ARM Cortex-A710/X2 erratum 2224489.
963 This option adds a workaround for ARM Cortex-A510 erratum #2441009.
976 bool "Cortex-A510: 2064142: workaround TRBE register writes while disabled"
980 This option adds the workaround for ARM Cortex-A510 erratum 2064142.
994 bool "Cortex-A510: 2038923: workaround TRBE corruption with enable"
998 This option adds the workaround for ARM Cortex-A510 erratum 2038923.
1017 bool "Cortex-A510: 1902691: workaround TRBE trace corruption"
1021 This option adds the workaround for ARM Cortex-A510 erratum 1902691.
1035 bool "Cortex-A510: 2457168: workaround for AMEVCNTR01 incrementing incorrectly"
1039 This option adds the workaround for ARM Cortex-A510 erratum 2457168.
1055 This option adds the workaround for ARM Cortex-A715 erratum 2645198.
1071 bool "Cortex-A520: 2966298: workaround for speculatively executed unprivileged load"
1075 This option adds the workaround for ARM Cortex-A520 erratum 2966298.
1085 bool "Cortex-A510: 3117295: workaround for speculatively executed unprivileged load"
1089 This option adds the workaround for ARM Cortex-A510 erratum 3117295.
1099 bool "Cortex-*/Neoverse-*: workaround for MSR SSBS not self-synchronizing"
1102 This option adds the workaround for the following errata:
1142 Enable workaround for errata 22375 and 24313.
1221 This option adds a workaround for Fujitsu-A64FX erratum E#010001.
1231 The workaround is to ensure these bits are clear in TCR_ELx.
1232 The workaround only affects the Fujitsu-A64FX.