Lines Matching refs:affected
455 The affected design reports FEAT_HAFDBS as not implemented in
488 the kernel if an affected CPU is detected.
510 the kernel if an affected CPU is detected.
533 only patch the kernel if an affected CPU is detected.
555 the kernel if an affected CPU is detected.
573 the kernel if an affected CPU is detected.
593 the kernel if an affected CPU is detected.
621 When running a compat (AArch32) userspace on an affected Cortex-A53
630 the kernel if an affected CPU is detected.
657 of hardware DBM locally on the affected cores. CPUs not affected by
722 …bool "Cortex-A55: Completion of affected memory accesses might not be guaranteed by completion of …
727 Under very rare circumstances, affected Cortex-A55 CPUs
732 Work around this by adding the affected CPUs to the list that needs
743 On the affected Cortex-A76 cores (r0p0 to r3p0), if a virtual
760 On the affected Cortex-A76 cores (r0p0 to r3p1), software stepping
817 is to not enable the feature on affected CPUs.
901 Workaround is to issue two TSB consecutively on affected cores.
916 Workaround is to issue two TSB consecutively on affected cores.
960 …bool "Cortex-A510: Completion of affected memory accesses might not be guaranteed by completion of…
965 Under very rare circumstances, affected Cortex-A510 CPUs
970 Work around this by adding the affected CPUs to the list that needs
988 is stopped and before performing a system register write to one of the affected
1028 affected cpus. The firmware must have disabled the access to TRBE for the kernel
1042 as the system counter. On affected Cortex-A510 cores AMEVCNTR01 increments
1045 Work around this problem by returning 0 when reading the affected counter in
1047 is the same to firmware disabling affected counters.
1077 On an affected Cortex-A520 core, a speculatively executed unprivileged
1091 On an affected Cortex-A510 core, a speculatively executed unprivileged
1126 On affected cores "MSR SSBS, #0" instructions may not affect