Lines Matching refs:errata

349 	  specific physical addresses or enable errata workarounds that may
542 	bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
551 	bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
560 	bool "ARM errata: Stale prediction on replaced interworking branch"
576 	bool "ARM errata: Processor deadlock when a false hazard is created"
592 	bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
607 	bool "ARM errata: DMB operation may be faulty"
623 	bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
641 	bool "ARM errata: LoUIS bit field in CLIDR register is incorrect"
652 	bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
664 	bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
680 	bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
695 	bool "ARM errata: possible faulty MMU translations following an ASID switch"
706 	bool "ARM errata: no automatic Store Buffer drain"
717 	bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
729 	bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
743 	bool "ARM errata: Read to DBGPRSR and DBGOSLSR may generate Undefined instruction"
754        bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock"
764 	bool "ARM errata: TLBI/DSB failure on Cortex-A15"
774 	bool "ARM errata: incorrect instructions may be executed from loop buffer"
783 	bool "ARM errata: A12: some seqs of opposed cond code instrs => deadlock or corruption"
792 	  This workaround for all both errata involves setting bit[12] of the
797 	bool "ARM errata: A12: sequence of VMOV to core registers might lead to a dead lock"
807 	bool "ARM errata: A12: DMB NSHST/ISHST mixed ... might cause deadlock"
816 	bool "ARM errata: A12: CPU might deadlock under some very rare internal conditions"
824 	bool "ARM errata: A17: DMB ST might fail to create order between stores"
833 	bool "ARM errata: A17: some seqs of opposed cond code instrs => deadlock or corruption"
841 	  config option from the A12 erratum due to the way errata are checked
845 	bool "ARM errata: A17: CPU might deadlock under some very rare internal conditions"
851 	  config option from the A12 erratum due to the way errata are checked
874 	bool "ARM errata: Cache maintenance by set/way operations can execute out of order"