Lines Matching refs:topckgen
174 <&topckgen CLK_TOP_UNIVPLL_D2>,
175 <&topckgen CLK_TOP_CCI400_SEL>,
176 <&topckgen CLK_TOP_VDEC_SEL>,
177 <&topckgen CLK_TOP_VCODECPLL>,
179 <&topckgen CLK_TOP_VENC_LT_SEL>,
180 <&topckgen CLK_TOP_VCODECPLL_370P5>;
189 assigned-clocks = <&topckgen CLK_TOP_VENC_LT_SEL>,
190 <&topckgen CLK_TOP_CCI400_SEL>,
191 <&topckgen CLK_TOP_VDEC_SEL>,
194 assigned-clock-parents = <&topckgen CLK_TOP_VCODECPLL_370P5>,
195 <&topckgen CLK_TOP_UNIVPLL_D2>,
196 <&topckgen CLK_TOP_VCODECPLL>;