108 	    uint32_t agp_status;  in pci_fill_capabilities_generic()  local
117 	    err = pci_device_cfg_read_u32( dev, & agp_status, cap_offset + 4 );  in pci_fill_capabilities_generic()
132 	    agp_info->rates = (agp_status & 0x07);  in pci_fill_capabilities_generic()
137 	    if ( (agp_status & 0x08) != 0 ) {  in pci_fill_capabilities_generic()
149 	    agp_info->fast_writes = (agp_status & 0x0010) != 0;  in pci_fill_capabilities_generic()
150 	    agp_info->addr64 =      (agp_status & 0x0020) != 0;  in pci_fill_capabilities_generic()
151 	    agp_info->htrans =      (agp_status & 0x0040) == 0;  in pci_fill_capabilities_generic()
152 	    agp_info->gart64 =      (agp_status & 0x0080) != 0;  in pci_fill_capabilities_generic()
153 	    agp_info->coherent =    (agp_status & 0x0100) != 0;  in pci_fill_capabilities_generic()
154 	    agp_info->sideband =    (agp_status & 0x0200) != 0;  in pci_fill_capabilities_generic()
155 	    agp_info->isochronus =  (agp_status & 0x10000) != 0;  in pci_fill_capabilities_generic()
157 	    agp_info->async_req_size = 4 + (1 << ((agp_status & 0xe000) >> 13));  in pci_fill_capabilities_generic()
158 	    agp_info->calibration_cycle_timing = ((agp_status & 0x1c00) >> 10);  in pci_fill_capabilities_generic()
159 	    agp_info->max_requests = 1 + ((agp_status & 0xff000000) >> 24);  in pci_fill_capabilities_generic()