59     uint8_t  buf[0x40];  in read_bridge_info()  local
81 	    pci_device_cfg_read( (struct pci_device *) priv, buf + 0x18, 0x18,  in read_bridge_info()
84 	    info->primary_bus = buf[0x18];  in read_bridge_info()
85 	    info->secondary_bus = buf[0x19];  in read_bridge_info()
86 	    info->subordinate_bus = buf[0x1a];  in read_bridge_info()
87 	    info->secondary_latency_timer = buf[0x1b];  in read_bridge_info()
89 	    info->io_type = buf[0x1c] & 0x0f;  in read_bridge_info()
90 	    info->io_base = (((uint32_t) (buf[0x1c] & 0x0f0)) << 8)  in read_bridge_info()
91 	      + (((uint32_t) buf[0x30]) << 16)  in read_bridge_info()
92 	      + (((uint32_t) buf[0x31]) << 24);  in read_bridge_info()
95 	      + (((uint32_t) (buf[0x1d] & 0x0f0)) << 8)  in read_bridge_info()
96 	      + (((uint32_t) buf[0x32]) << 16)  in read_bridge_info()
97 	      + (((uint32_t) buf[0x33]) << 24);  in read_bridge_info()
99 	    info->mem_type = buf[0x20] & 0x0f;  in read_bridge_info()
100 	    info->mem_base = (((uint32_t) (buf[0x20] & 0x0f0)) << 16)  in read_bridge_info()
101 	      + (((uint32_t) buf[0x21]) << 24);  in read_bridge_info()
104 	      + (((uint32_t) (buf[0x22] & 0x0f0)) << 16)  in read_bridge_info()
105 	      + (((uint32_t) buf[0x23]) << 24);  in read_bridge_info()
107 	    info->prefetch_mem_type = buf[0x24] & 0x0f;  in read_bridge_info()
108 	    info->prefetch_mem_base = (((uint64_t) (buf[0x24] & 0x0f0)) << 16)  in read_bridge_info()
109 	      + (((uint64_t) buf[0x25]) << 24)  in read_bridge_info()
110 	      + (((uint64_t) buf[0x28]) << 32)  in read_bridge_info()
111 	      + (((uint64_t) buf[0x29]) << 40)  in read_bridge_info()
112 	      + (((uint64_t) buf[0x2a]) << 48)  in read_bridge_info()
113 	      + (((uint64_t) buf[0x2b]) << 56);  in read_bridge_info()
116 	      + (((uint64_t) (buf[0x26] & 0x0f0)) << 16)  in read_bridge_info()
117 	      + (((uint64_t) buf[0x27]) << 24)  in read_bridge_info()
118 	      + (((uint64_t) buf[0x2c]) << 32)  in read_bridge_info()
119 	      + (((uint64_t) buf[0x2d]) << 40)  in read_bridge_info()
120 	      + (((uint64_t) buf[0x2e]) << 48)  in read_bridge_info()
121 	      + (((uint64_t) buf[0x2f]) << 56);  in read_bridge_info()
123 	    info->bridge_control = ((uint16_t) buf[0x3e])  in read_bridge_info()
124 	      + (((uint16_t) buf[0x3f]) << 8);  in read_bridge_info()
126 	    info->secondary_status = ((uint16_t) buf[0x1e])  in read_bridge_info()
127 	      + (((uint16_t) buf[0x1f]) << 8);  in read_bridge_info()
139 	    pci_device_cfg_read( (struct pci_device *) priv, buf + 0x16, 0x16,  in read_bridge_info()
142 	    info->primary_bus = buf[0x18];  in read_bridge_info()
143 	    info->card_bus = buf[0x19];  in read_bridge_info()
144 	    info->subordinate_bus = buf[0x1a];  in read_bridge_info()
145 	    info->cardbus_latency_timer = buf[0x1b];  in read_bridge_info()
147 	    info->mem[0].base = (((uint32_t) buf[0x1c]))  in read_bridge_info()
148 	      + (((uint32_t) buf[0x1d]) << 8)  in read_bridge_info()
149 	      + (((uint32_t) buf[0x1e]) << 16)  in read_bridge_info()
150 	      + (((uint32_t) buf[0x1f]) << 24);  in read_bridge_info()
152 	    info->mem[0].limit = (((uint32_t) buf[0x20]))  in read_bridge_info()
153 	      + (((uint32_t) buf[0x21]) << 8)  in read_bridge_info()
154 	      + (((uint32_t) buf[0x22]) << 16)  in read_bridge_info()
155 	      + (((uint32_t) buf[0x23]) << 24);  in read_bridge_info()
157 	    info->mem[1].base = (((uint32_t) buf[0x24]))  in read_bridge_info()
158 	      + (((uint32_t) buf[0x25]) << 8)  in read_bridge_info()
159 	      + (((uint32_t) buf[0x26]) << 16)  in read_bridge_info()
160 	      + (((uint32_t) buf[0x27]) << 24);  in read_bridge_info()
162 	    info->mem[1].limit = (((uint32_t) buf[0x28]))  in read_bridge_info()
163 	      + (((uint32_t) buf[0x29]) << 8)  in read_bridge_info()
164 	      + (((uint32_t) buf[0x2a]) << 16)  in read_bridge_info()
165 	      + (((uint32_t) buf[0x2b]) << 24);  in read_bridge_info()
167 	    info->io[0].base = (((uint32_t) buf[0x2c]))  in read_bridge_info()
168 	      + (((uint32_t) buf[0x2d]) << 8)  in read_bridge_info()
169 	      + (((uint32_t) buf[0x2e]) << 16)  in read_bridge_info()
170 	      + (((uint32_t) buf[0x2f]) << 24);  in read_bridge_info()
172 	    info->io[0].limit = (((uint32_t) buf[0x30]))  in read_bridge_info()
173 	      + (((uint32_t) buf[0x31]) << 8)  in read_bridge_info()
174 	      + (((uint32_t) buf[0x32]) << 16)  in read_bridge_info()
175 	      + (((uint32_t) buf[0x33]) << 24);  in read_bridge_info()
177 	    info->io[1].base = (((uint32_t) buf[0x34]))  in read_bridge_info()
178 	      + (((uint32_t) buf[0x35]) << 8)  in read_bridge_info()
179 	      + (((uint32_t) buf[0x36]) << 16)  in read_bridge_info()
180 	      + (((uint32_t) buf[0x37]) << 24);  in read_bridge_info()
182 	    info->io[1].limit = (((uint32_t) buf[0x38]))  in read_bridge_info()
183 	      + (((uint32_t) buf[0x39]) << 8)  in read_bridge_info()
184 	      + (((uint32_t) buf[0x3a]) << 16)  in read_bridge_info()
185 	      + (((uint32_t) buf[0x3b]) << 24);  in read_bridge_info()
187 	    info->secondary_status = ((uint16_t) buf[0x16])  in read_bridge_info()
188 	      + (((uint16_t) buf[0x17]) << 8);  in read_bridge_info()
190 	    info->bridge_control = ((uint16_t) buf[0x3e])  in read_bridge_info()
191 	      + (((uint16_t) buf[0x3f]) << 8);  in read_bridge_info()