157 static void		ural_write(struct ural_softc *, uint16_t, uint16_t);
689 			ural_write(sc, RAL_TXRX_CSR19, 0);  in ural_newstate()
692 			ural_write(sc, RAL_MAC_CSR20, 0);  in ural_newstate()
727 		ural_write(sc, RAL_MAC_CSR20, 1);  in ural_newstate()
1441 ural_write(struct ural_softc *sc, uint16_t reg, uint16_t val)  in ural_write()  function
1496 	ural_write(sc, RAL_PHY_CSR7, tmp);  in ural_bbp_write()
1506 	ural_write(sc, RAL_PHY_CSR7, val);  in ural_bbp_read()
1540 	ural_write(sc, RAL_PHY_CSR9,  tmp & 0xffff);  in ural_rf_write()
1541 	ural_write(sc, RAL_PHY_CSR10, tmp >> 16);  in ural_rf_write()
1555 	ural_write(sc, RAL_TXRX_CSR19, 0);  in ural_scan_start()
1740 	ural_write(sc, RAL_TXRX_CSR19, 0);  in ural_enable_tsf_sync()
1743 	ural_write(sc, RAL_TXRX_CSR18, tmp);  in ural_enable_tsf_sync()
1748 	ural_write(sc, RAL_TXRX_CSR20, tmp);  in ural_enable_tsf_sync()
1756 	ural_write(sc, RAL_TXRX_CSR19, tmp);  in ural_enable_tsf_sync()
1765 	ural_write(sc, RAL_TXRX_CSR19, 0);  in ural_enable_tsf()
1766 	ural_write(sc, RAL_TXRX_CSR19, RAL_ENABLE_TSF | RAL_ENABLE_TSF_SYNC(2));  in ural_enable_tsf()
1790 	ural_write(sc, RAL_MAC_CSR10, slottime);  in ural_update_slot()
1791 	ural_write(sc, RAL_MAC_CSR11, sifs);  in ural_update_slot()
1792 	ural_write(sc, RAL_MAC_CSR12, eifs);  in ural_update_slot()
1807 	ural_write(sc, RAL_TXRX_CSR10, tmp);  in ural_set_txpreamble()
1817 		ural_write(sc, RAL_TXRX_CSR11, 0x150);  in ural_set_basicrates()
1820 		ural_write(sc, RAL_TXRX_CSR11, 0x15f);  in ural_set_basicrates()
1823 		ural_write(sc, RAL_TXRX_CSR11, 0x3);  in ural_set_basicrates()
1833 	ural_write(sc, RAL_MAC_CSR5, tmp);  in ural_set_bssid()
1836 	ural_write(sc, RAL_MAC_CSR6, tmp);  in ural_set_bssid()
1839 	ural_write(sc, RAL_MAC_CSR7, tmp);  in ural_set_bssid()
1850 	ural_write(sc, RAL_MAC_CSR2, tmp);  in ural_set_macaddr()
1853 	ural_write(sc, RAL_MAC_CSR3, tmp);  in ural_set_macaddr()
1856 	ural_write(sc, RAL_MAC_CSR4, tmp);  in ural_set_macaddr()
1872 	ural_write(sc, RAL_TXRX_CSR2, tmp);  in ural_setpromisc()
1985 	ural_write(sc, RAL_PHY_CSR5, tmp | (tx & 0x7));  in ural_set_txantenna()
1988 	ural_write(sc, RAL_PHY_CSR6, tmp | (tx & 0x7));  in ural_set_txantenna()
2022 	ural_write(sc, 0x308, 0x00f0);	/* XXX magic */  in ural_init()
2028 		ural_write(sc, ural_def_mac[i].reg, ural_def_mac[i].val);  in ural_init()
2046 	ural_write(sc, RAL_MAC_CSR1, RAL_HOST_READY);  in ural_init()
2049 	ural_write(sc, RAL_TXRX_CSR11, 0x15f);  in ural_init()
2078 	ural_write(sc, RAL_TXRX_CSR2, tmp);  in ural_init()
2107 	ural_write(sc, RAL_TXRX_CSR2, RAL_DISABLE_RX);  in ural_stop()
2109 	ural_write(sc, RAL_MAC_CSR1, RAL_RESET_ASIC | RAL_RESET_BBP);  in ural_stop()
2112 	ural_write(sc, RAL_MAC_CSR1, 0);  in ural_stop()