Lines Matching refs:temp
245 uint32_t temp; in xhci_reset_command_queue_locked() local
249 temp = XREAD4(sc, oper, XHCI_CRCR_LO); in xhci_reset_command_queue_locked()
250 if (temp & XHCI_CRCR_LO_CRR) { in xhci_reset_command_queue_locked()
252 temp &= ~(XHCI_CRCR_LO_CS | XHCI_CRCR_LO_CA); in xhci_reset_command_queue_locked()
261 XWRITE4(sc, oper, XHCI_CRCR_LO, temp | XHCI_CRCR_LO_CS); in xhci_reset_command_queue_locked()
264 XWRITE4(sc, oper, XHCI_CRCR_LO, temp | XHCI_CRCR_LO_CA); in xhci_reset_command_queue_locked()
271 temp = XREAD4(sc, oper, XHCI_CRCR_LO); in xhci_reset_command_queue_locked()
272 if (temp & XHCI_CRCR_LO_CRR) { in xhci_reset_command_queue_locked()
310 uint32_t temp; in xhci_start_controller() local
330 temp = XREAD4(sc, oper, XHCI_USBSTS); in xhci_start_controller()
333 XWRITE4(sc, oper, XHCI_USBSTS, temp); in xhci_start_controller()
408 temp = XREAD4(sc, runt, XHCI_IMAN(0)); in xhci_start_controller()
409 temp |= XHCI_IMAN_INTR_ENA; in xhci_start_controller()
410 XWRITE4(sc, runt, XHCI_IMAN(0), temp); in xhci_start_controller()
431 temp = XREAD4(sc, oper, XHCI_USBSTS) & XHCI_STS_HCH; in xhci_start_controller()
432 if (!temp) in xhci_start_controller()
435 if (temp) { in xhci_start_controller()
455 uint32_t temp; in xhci_halt_controller() local
470 temp = XREAD4(sc, oper, XHCI_USBSTS) & XHCI_STS_HCH; in xhci_halt_controller()
471 if (temp) in xhci_halt_controller()
475 if (!temp) { in xhci_halt_controller()
485 uint32_t temp = 0; in xhci_reset_controller() local
495 temp = (XREAD4(sc, oper, XHCI_USBCMD) & XHCI_CMD_HCRST) | in xhci_reset_controller()
497 if (!temp) in xhci_reset_controller()
501 if (temp) { in xhci_reset_controller()
512 uint32_t temp; in xhci_init() local
551 temp = XREAD4(sc, capa, XHCI_HCSPARAMS0); in xhci_init()
553 DPRINTF("HCS0 = 0x%08x\n", temp); in xhci_init()
556 if (XHCI_HCS0_CSZ(temp)) { in xhci_init()
563 sc->sc_bus.dma_bits = (XHCI_HCS0_AC64(temp) && in xhci_init()
572 temp = XREAD4(sc, capa, XHCI_HCSPARAMS1); in xhci_init()
575 sc->sc_noport = XHCI_HCS1_N_PORTS(temp); in xhci_init()
583 sc->sc_noslot = XHCI_HCS1_DEVSLOT_MAX(temp); in xhci_init()
590 temp = XREAD4(sc, capa, XHCI_HCSPARAMS2); in xhci_init()
592 DPRINTF("HCS2=0x%08x\n", temp); in xhci_init()
595 sc->sc_ist = XHCI_HCS2_IST(temp); in xhci_init()
598 sc->sc_noscratch = XHCI_HCS2_SPB_MAX(temp); in xhci_init()
609 sc->sc_erst_max = 1U << XHCI_HCS2_ERST_MAX(temp); in xhci_init()
613 temp = XREAD4(sc, capa, XHCI_HCSPARAMS3); in xhci_init()
616 sc->sc_exit_lat_max = XHCI_HCS3_U1_DEL(temp) + in xhci_init()
617 XHCI_HCS3_U2_DEL(temp) + 250 /* us */; in xhci_init()
857 uint32_t temp; in xhci_check_transfer() local
868 temp = le32toh(trb->dwTrb2); in xhci_check_transfer()
870 remainder = XHCI_TRB_2_REM_GET(temp); in xhci_check_transfer()
871 status = XHCI_TRB_2_ERROR_GET(temp); in xhci_check_transfer()
873 temp = le32toh(trb->dwTrb3); in xhci_check_transfer()
874 epno = XHCI_TRB_3_EP_GET(temp); in xhci_check_transfer()
875 index = XHCI_TRB_3_SLOT_GET(temp); in xhci_check_transfer()
939 temp = le32toh(td->td_trb[i].dwTrb2); in xhci_check_transfer()
940 remainder += XHCI_TRB_2_BYTES_GET(temp); in xhci_check_transfer()
1035 uint32_t temp; in xhci_interrupt_poll() local
1056 temp = le32toh(phwr->hwr_events[i].dwTrb3); in xhci_interrupt_poll()
1058 k = (temp & XHCI_TRB_3_CYCLE_BIT) ? 1 : 0; in xhci_interrupt_poll()
1063 event = XHCI_TRB_3_TYPE_GET(temp); in xhci_interrupt_poll()
1123 uint32_t temp; in xhci_do_command() local
1155 temp = trb->dwTrb3; in xhci_do_command()
1158 temp |= htole32(XHCI_TRB_3_CYCLE_BIT); in xhci_do_command()
1160 temp &= ~htole32(XHCI_TRB_3_CYCLE_BIT); in xhci_do_command()
1162 temp &= ~htole32(XHCI_TRB_3_TC_BIT); in xhci_do_command()
1164 phwr->hwr_commands[i].dwTrb3 = temp; in xhci_do_command()
1177 temp = htole32(XHCI_TRB_3_TC_BIT | in xhci_do_command()
1181 temp = htole32(XHCI_TRB_3_TC_BIT | in xhci_do_command()
1185 phwr->hwr_commands[i].dwTrb3 = temp; in xhci_do_command()
1221 temp = le32toh(trb->dwTrb3); in xhci_do_command()
1228 if (XHCI_TRB_3_TYPE_GET(temp) == XHCI_TRB_TYPE_ADDRESS_DEVICE && in xhci_do_command()
1229 (temp & XHCI_TRB_3_BSR_BIT) == 0) { in xhci_do_command()
1243 temp = le32toh(sc->sc_cmd_result[0]); in xhci_do_command()
1244 if (XHCI_TRB_2_ERROR_GET(temp) != XHCI_TRB_ERROR_SUCCESS) in xhci_do_command()
1261 uint32_t temp;
1267 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NOOP);
1269 trb.dwTrb3 = htole32(temp);
1279 uint32_t temp; in xhci_cmd_enable_slot() local
1292 temp = le32toh(trb.dwTrb3); in xhci_cmd_enable_slot()
1294 *pslot = XHCI_TRB_3_SLOT_GET(temp); in xhci_cmd_enable_slot()
1304 uint32_t temp; in xhci_cmd_disable_slot() local
1310 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_DISABLE_SLOT) | in xhci_cmd_disable_slot()
1313 trb.dwTrb3 = htole32(temp); in xhci_cmd_disable_slot()
1323 uint32_t temp; in xhci_cmd_set_address() local
1329 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ADDRESS_DEVICE) | in xhci_cmd_set_address()
1333 temp |= XHCI_TRB_3_BSR_BIT; in xhci_cmd_set_address()
1335 trb.dwTrb3 = htole32(temp); in xhci_cmd_set_address()
1349 uint32_t temp; in xhci_set_address() local
1423 temp = le32toh(sc->sc_cmd_result[0]); in xhci_set_address()
1425 XHCI_TRB_2_ERROR_GET(temp) == in xhci_set_address()
1444 temp = le32toh(slot->dwSctx3); in xhci_set_address()
1445 udev->address = XHCI_SCTX_3_DEV_ADDR_GET(temp); in xhci_set_address()
1473 uint32_t temp; in xhci_cmd_configure_ep() local
1479 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_CONFIGURE_EP) | in xhci_cmd_configure_ep()
1485 temp |= XHCI_TRB_3_DCEP_BIT; in xhci_cmd_configure_ep()
1488 trb.dwTrb3 = htole32(temp); in xhci_cmd_configure_ep()
1498 uint32_t temp; in xhci_cmd_evaluate_ctx() local
1504 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_EVALUATE_CTX) | in xhci_cmd_evaluate_ctx()
1506 trb.dwTrb3 = htole32(temp); in xhci_cmd_evaluate_ctx()
1516 uint32_t temp; in xhci_cmd_reset_ep() local
1522 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_RESET_EP) | in xhci_cmd_reset_ep()
1527 temp |= XHCI_TRB_3_PRSV_BIT; in xhci_cmd_reset_ep()
1529 trb.dwTrb3 = htole32(temp); in xhci_cmd_reset_ep()
1539 uint32_t temp; in xhci_cmd_set_tr_dequeue_ptr() local
1545 temp = XHCI_TRB_2_STREAM_SET(stream_id); in xhci_cmd_set_tr_dequeue_ptr()
1546 trb.dwTrb2 = htole32(temp); in xhci_cmd_set_tr_dequeue_ptr()
1548 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_SET_TR_DEQUEUE) | in xhci_cmd_set_tr_dequeue_ptr()
1551 trb.dwTrb3 = htole32(temp); in xhci_cmd_set_tr_dequeue_ptr()
1561 uint32_t temp; in xhci_cmd_stop_ep() local
1567 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_STOP_EP) | in xhci_cmd_stop_ep()
1572 temp |= XHCI_TRB_3_SUSP_EP_BIT; in xhci_cmd_stop_ep()
1574 trb.dwTrb3 = htole32(temp); in xhci_cmd_stop_ep()
1583 uint32_t temp; in xhci_cmd_reset_dev() local
1589 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_RESET_DEVICE) | in xhci_cmd_reset_dev()
1592 trb.dwTrb3 = htole32(temp); in xhci_cmd_reset_dev()
1604 uint32_t temp; in xhci_interrupt() local
1616 temp = XREAD4(sc, runt, XHCI_IMAN(0)); in xhci_interrupt()
1619 if (temp & XHCI_IMAN_INTR_PEND) in xhci_interrupt()
1620 XWRITE4(sc, runt, XHCI_IMAN(0), temp); in xhci_interrupt()
1676 xhci_setup_generic_chain_sub(struct xhci_std_temp *temp) in xhci_setup_generic_chain_sub() argument
1694 shortpkt_old = temp->shortpkt; in xhci_setup_generic_chain_sub()
1695 len_old = temp->len; in xhci_setup_generic_chain_sub()
1701 td = temp->td; in xhci_setup_generic_chain_sub()
1702 td_next = td_first = temp->td_next; in xhci_setup_generic_chain_sub()
1705 if (temp->len == 0) { in xhci_setup_generic_chain_sub()
1706 if (temp->shortpkt) in xhci_setup_generic_chain_sub()
1711 temp->shortpkt = 1; in xhci_setup_generic_chain_sub()
1715 average = temp->average; in xhci_setup_generic_chain_sub()
1717 if (temp->len < average) { in xhci_setup_generic_chain_sub()
1718 if (temp->len % temp->max_packet_size) { in xhci_setup_generic_chain_sub()
1719 temp->shortpkt = 1; in xhci_setup_generic_chain_sub()
1721 average = temp->len; in xhci_setup_generic_chain_sub()
1738 temp->len -= average; in xhci_setup_generic_chain_sub()
1750 temp->len -= average; in xhci_setup_generic_chain_sub()
1756 if (temp->trb_type == XHCI_TRB_TYPE_SETUP_STAGE) { in xhci_setup_generic_chain_sub()
1764 usbd_copy_out(temp->pc, temp->offset + buf_offset, in xhci_setup_generic_chain_sub()
1801 usbd_get_page(temp->pc, temp->offset + in xhci_setup_generic_chain_sub()
1817 temp->max_packet_size); in xhci_setup_generic_chain_sub()
1835 switch (temp->trb_type) { in xhci_setup_generic_chain_sub()
1838 XHCI_TRB_3_TBC_SET(temp->tbc) | in xhci_setup_generic_chain_sub()
1839 XHCI_TRB_3_TLBPC_SET(temp->tlbpc); in xhci_setup_generic_chain_sub()
1842 } else if (temp->do_isoc_sync != 0) { in xhci_setup_generic_chain_sub()
1843 temp->do_isoc_sync = 0; in xhci_setup_generic_chain_sub()
1846 XHCI_TRB_3_FRID_SET(temp->isoc_frame / 8); in xhci_setup_generic_chain_sub()
1852 if (temp->direction == UE_DIR_IN) in xhci_setup_generic_chain_sub()
1858 if (temp->direction == UE_DIR_IN) in xhci_setup_generic_chain_sub()
1868 temp->trb_type = XHCI_TRB_TYPE_NORMAL; in xhci_setup_generic_chain_sub()
1873 if (temp->direction == UE_DIR_IN) in xhci_setup_generic_chain_sub()
1879 if (temp->direction == UE_DIR_IN) in xhci_setup_generic_chain_sub()
1942 if (temp->last_frame) { in xhci_setup_generic_chain_sub()
1950 temp->shortpkt = shortpkt_old; in xhci_setup_generic_chain_sub()
1951 temp->len = len_old; in xhci_setup_generic_chain_sub()
1959 if (temp->step_td != 0) { in xhci_setup_generic_chain_sub()
1973 temp->td = td; in xhci_setup_generic_chain_sub()
1974 temp->td_next = td_next; in xhci_setup_generic_chain_sub()
1980 struct xhci_std_temp temp; in xhci_setup_generic_chain() local
1986 temp.do_isoc_sync = 0; in xhci_setup_generic_chain()
1987 temp.step_td = 0; in xhci_setup_generic_chain()
1988 temp.tbc = 0; in xhci_setup_generic_chain()
1989 temp.tlbpc = 0; in xhci_setup_generic_chain()
1990 temp.average = xfer->max_hc_frame_size; in xhci_setup_generic_chain()
1991 temp.max_packet_size = xfer->max_packet_size; in xhci_setup_generic_chain()
1992 temp.sc = XHCI_BUS2SC(xfer->xroot->bus); in xhci_setup_generic_chain()
1993 temp.pc = NULL; in xhci_setup_generic_chain()
1994 temp.last_frame = 0; in xhci_setup_generic_chain()
1995 temp.offset = 0; in xhci_setup_generic_chain()
1996 temp.multishort = xfer->flags_int.isochronous_xfr || in xhci_setup_generic_chain()
2006 temp.td = NULL; in xhci_setup_generic_chain()
2007 temp.td_next = td; in xhci_setup_generic_chain()
2030 x = XREAD4(temp.sc, runt, XHCI_MFINDEX); in xhci_setup_generic_chain()
2032 DPRINTF("MFINDEX=0x%08x IST=0x%x\n", x, temp.sc->sc_ist); in xhci_setup_generic_chain()
2037 temp.isoc_delta = 8; /* 1ms */ in xhci_setup_generic_chain()
2041 temp.isoc_delta = 1U << shift; in xhci_setup_generic_chain()
2046 if (temp.sc->sc_ist & 8) in xhci_setup_generic_chain()
2047 y = (temp.sc->sc_ist & 7) << 3; in xhci_setup_generic_chain()
2049 y = (temp.sc->sc_ist & 7); in xhci_setup_generic_chain()
2055 DPRINTFN(3, "IST(%d) is too big!\n", temp.sc->sc_ist); in xhci_setup_generic_chain()
2074 xfer, x, y, 8, XHCI_MFINDEX_GET(-1), &temp.isoc_frame)) { in xhci_setup_generic_chain()
2076 temp.do_isoc_sync = 1; in xhci_setup_generic_chain()
2078 DPRINTFN(3, "start next=%d\n", temp.isoc_frame); in xhci_setup_generic_chain()
2082 temp.trb_type = XHCI_TRB_TYPE_ISOCH; in xhci_setup_generic_chain()
2088 temp.len = xfer->frlengths[0]; in xhci_setup_generic_chain()
2089 temp.pc = xfer->frbuffers + 0; in xhci_setup_generic_chain()
2090 temp.shortpkt = temp.len ? 1 : 0; in xhci_setup_generic_chain()
2091 temp.trb_type = XHCI_TRB_TYPE_SETUP_STAGE; in xhci_setup_generic_chain()
2092 temp.direction = 0; in xhci_setup_generic_chain()
2098 temp.last_frame = 1; in xhci_setup_generic_chain()
2101 xhci_setup_generic_chain_sub(&temp); in xhci_setup_generic_chain()
2105 temp.isoc_delta = 0; in xhci_setup_generic_chain()
2106 temp.isoc_frame = 0; in xhci_setup_generic_chain()
2107 temp.trb_type = xfer->flags_int.control_did_data ? in xhci_setup_generic_chain()
2112 temp.isoc_delta = 0; in xhci_setup_generic_chain()
2113 temp.isoc_frame = 0; in xhci_setup_generic_chain()
2114 temp.trb_type = XHCI_TRB_TYPE_NORMAL; in xhci_setup_generic_chain()
2119 temp.pc = xfer->frbuffers + x; in xhci_setup_generic_chain()
2121 temp.direction = UE_GET_DIR(xfer->endpointno); in xhci_setup_generic_chain()
2127 temp.len = xfer->frlengths[x]; in xhci_setup_generic_chain()
2128 temp.step_td = ((xfer->endpointno & UE_DIR_IN) && in xhci_setup_generic_chain()
2129 x != 0 && temp.multishort == 0); in xhci_setup_generic_chain()
2137 temp.last_frame = 1; in xhci_setup_generic_chain()
2139 temp.last_frame = 1; in xhci_setup_generic_chain()
2142 if (temp.len == 0) { in xhci_setup_generic_chain()
2145 temp.shortpkt = 0; in xhci_setup_generic_chain()
2147 temp.tbc = 0; in xhci_setup_generic_chain()
2148 temp.tlbpc = mult - 1; in xhci_setup_generic_chain()
2158 temp.shortpkt = 1; in xhci_setup_generic_chain()
2162 if (temp.len > xfer->max_frame_size) in xhci_setup_generic_chain()
2163 temp.len = xfer->max_frame_size; in xhci_setup_generic_chain()
2166 tdpc = howmany(temp.len, xfer->max_packet_size); in xhci_setup_generic_chain()
2168 temp.tbc = howmany(tdpc, mult) - 1; in xhci_setup_generic_chain()
2169 temp.tlbpc = (tdpc % mult); in xhci_setup_generic_chain()
2171 if (temp.tlbpc == 0) in xhci_setup_generic_chain()
2172 temp.tlbpc = mult - 1; in xhci_setup_generic_chain()
2174 temp.tlbpc--; in xhci_setup_generic_chain()
2178 temp.shortpkt = xfer->flags.force_short_xfer ? 0 : 1; in xhci_setup_generic_chain()
2181 xhci_setup_generic_chain_sub(&temp); in xhci_setup_generic_chain()
2184 temp.offset += xfer->frlengths[x - 1]; in xhci_setup_generic_chain()
2185 temp.isoc_frame += temp.isoc_delta; in xhci_setup_generic_chain()
2188 temp.pc = xfer->frbuffers + x; in xhci_setup_generic_chain()
2200 if (xhcictlstep || temp.sc->sc_ctlstep) { in xhci_setup_generic_chain()
2207 temp.step_td = (xfer->nframes != 0); in xhci_setup_generic_chain()
2209 temp.step_td = 0; in xhci_setup_generic_chain()
2211 temp.direction = UE_GET_DIR(xfer->endpointno) ^ UE_DIR_IN; in xhci_setup_generic_chain()
2212 temp.len = 0; in xhci_setup_generic_chain()
2213 temp.pc = NULL; in xhci_setup_generic_chain()
2214 temp.shortpkt = 0; in xhci_setup_generic_chain()
2215 temp.last_frame = 1; in xhci_setup_generic_chain()
2216 temp.trb_type = XHCI_TRB_TYPE_STATUS_STAGE; in xhci_setup_generic_chain()
2218 xhci_setup_generic_chain_sub(&temp); in xhci_setup_generic_chain()
2221 td = temp.td; in xhci_setup_generic_chain()
2254 uint32_t temp; in xhci_configure_mask() local
2296 temp = le32toh(slot->dwSctx0); in xhci_configure_mask()
2297 temp &= ~XHCI_SCTX_0_CTX_NUM_SET(31); in xhci_configure_mask()
2298 temp |= XHCI_SCTX_0_CTX_NUM_SET(x + 1); in xhci_configure_mask()
2299 slot->dwSctx0 = htole32(temp); in xhci_configure_mask()
2316 uint32_t temp; in xhci_configure_endpoint() local
2354 temp = XHCI_EPCTX_0_EPSTATE_SET(0) | in xhci_configure_endpoint()
2361 temp = XHCI_EPCTX_0_EPSTATE_SET(0) | in xhci_configure_endpoint()
2382 temp |= XHCI_EPCTX_0_IVAL_SET(fps_shift); in xhci_configure_endpoint()
2385 temp |= XHCI_EPCTX_0_IVAL_SET(fps_shift); in xhci_configure_endpoint()
2391 temp |= XHCI_EPCTX_0_MULT_SET(mult - 1); in xhci_configure_endpoint()
2402 endp->dwEpCtx0 = htole32(temp); in xhci_configure_endpoint()
2404 temp = in xhci_configure_endpoint()
2416 temp |= XHCI_EPCTX_1_CERR_SET(3); in xhci_configure_endpoint()
2420 temp |= XHCI_EPCTX_1_EPTYPE_SET(4); in xhci_configure_endpoint()
2423 temp |= XHCI_EPCTX_1_EPTYPE_SET(1); in xhci_configure_endpoint()
2426 temp |= XHCI_EPCTX_1_EPTYPE_SET(2); in xhci_configure_endpoint()
2429 temp |= XHCI_EPCTX_1_EPTYPE_SET(3); in xhci_configure_endpoint()
2435 temp |= XHCI_EPCTX_1_EPTYPE_SET(4); in xhci_configure_endpoint()
2437 endp->dwEpCtx1 = htole32(temp); in xhci_configure_endpoint()
2443 temp = XHCI_EPCTX_4_MAX_ESIT_PAYLOAD_SET(max_frame_size) | in xhci_configure_endpoint()
2448 temp = XHCI_EPCTX_4_AVG_TRB_LEN_SET(8); in xhci_configure_endpoint()
2451 temp = XHCI_EPCTX_4_AVG_TRB_LEN_SET(XHCI_PAGE_SIZE); in xhci_configure_endpoint()
2455 endp->dwEpCtx4 = htole32(temp); in xhci_configure_endpoint()
2478 uint64_t temp; in xhci_configure_endpoint_by_xfer() local
2484 temp = pepext->physaddr + in xhci_configure_endpoint_by_xfer()
2490 XHCI_MAX_STREAMS) + x].qwTrb0 = htole64(temp); in xhci_configure_endpoint_by_xfer()
2516 uint32_t temp; in xhci_configure_device() local
2563 temp = XHCI_SCTX_0_ROUTE_SET(route) | in xhci_configure_device()
2569 temp |= XHCI_SCTX_0_SPEED_SET(2); in xhci_configure_device()
2574 temp |= XHCI_SCTX_0_MTT_SET(1); in xhci_configure_device()
2578 temp |= XHCI_SCTX_0_SPEED_SET(3); in xhci_configure_device()
2582 temp |= XHCI_SCTX_0_MTT_SET(1); in xhci_configure_device()
2586 temp |= XHCI_SCTX_0_SPEED_SET(1); in xhci_configure_device()
2591 temp |= XHCI_SCTX_0_MTT_SET(1); in xhci_configure_device()
2595 temp |= XHCI_SCTX_0_SPEED_SET(4); in xhci_configure_device()
2604 temp |= XHCI_SCTX_0_HUB_SET(1); in xhci_configure_device()
2606 slot->dwSctx0 = htole32(temp); in xhci_configure_device()
2608 temp = XHCI_SCTX_1_RH_PORT_SET(rh_port); in xhci_configure_device()
2611 temp |= XHCI_SCTX_1_NUM_PORTS_SET( in xhci_configure_device()
2615 slot->dwSctx1 = htole32(temp); in xhci_configure_device()
2617 temp = XHCI_SCTX_2_IRQ_TARGET_SET(0); in xhci_configure_device()
2620 temp |= XHCI_SCTX_2_TT_THINK_TIME_SET( in xhci_configure_device()
2631 temp |= XHCI_SCTX_2_TT_HUB_SID_SET( in xhci_configure_device()
2633 temp |= XHCI_SCTX_2_TT_PORT_NUM_SET( in xhci_configure_device()
2641 slot->dwSctx2 = htole32(temp); in xhci_configure_device()
2647 temp = XHCI_SCTX_3_DEV_ADDR_SET(0) | in xhci_configure_device()
2650 slot->dwSctx3 = htole32(temp); in xhci_configure_device()
3254 sc->sc_hub_desc.temp[0] = sc->sc_conf; in xhci_roothub_exec()
3305 sc->sc_hub_desc.temp, in xhci_roothub_exec()
3306 sizeof(sc->sc_hub_desc.temp), in xhci_roothub_exec()
3317 sc->sc_hub_desc.temp[0] = 0; in xhci_roothub_exec()
3462 memset(sc->sc_hub_desc.temp, 0, 16); in xhci_roothub_exec()
3744 uint32_t temp; in xhci_get_endpoint_state() local
3755 temp = le32toh(endp->dwEpCtx0); in xhci_get_endpoint_state()
3757 return (XHCI_EPCTX_0_EPSTATE_GET(temp)); in xhci_get_endpoint_state()
4104 uint8_t temp; in xhci_device_init() local
4118 err = xhci_cmd_enable_slot(sc, &temp); in xhci_device_init()
4125 if (temp > sc->sc_noslot) { in xhci_device_init()
4130 if (sc->sc_hw.devs[temp].state != XHCI_ST_DISABLED) { in xhci_device_init()
4131 DPRINTF("slot %u already allocated.\n", temp); in xhci_device_init()
4138 udev->controller_slot_id = temp; in xhci_device_init()
4142 memset(&sc->sc_hw.devs[temp], 0, sizeof(sc->sc_hw.devs[0])); in xhci_device_init()
4146 sc->sc_hw.devs[temp].state = XHCI_ST_ENABLED; in xhci_device_init()