53 #define	UART_CTRL		0x08		/* Control Register */  macro
181 	ctrl = uart_getreg(bas, UART_CTRL);  in uart_mvebu_param()
182 	uart_setreg(bas, UART_CTRL, ctrl | CTRL_TX_FIFO_RST | CTRL_RX_FIFO_RST |  in uart_mvebu_param()
220 	uart_setreg(bas, UART_CTRL, ctrl);  in uart_mvebu_param()
234 	uart_setreg(bas, UART_CTRL, uart_getreg(bas, UART_CTRL) &  in uart_mvebu_init()
337 	ctrl = uart_getreg(bas, UART_CTRL);  in uart_mvebu_bus_attach()
344 	uart_setreg(bas, UART_CTRL, ctrl);  in uart_mvebu_bus_attach()
367 	ctrl = uart_getreg(bas, UART_CTRL);  in uart_mvebu_bus_flush()
371 		uart_setreg(bas, UART_CTRL, ctrl | CTRL_RX_FIFO_RST);  in uart_mvebu_bus_flush()
376 		uart_setreg(bas, UART_CTRL, ctrl | CTRL_TX_FIFO_RST);  in uart_mvebu_bus_flush()
387 		uart_setreg(bas, UART_CTRL, ctrl);  in uart_mvebu_bus_flush()
413 		ctrl = uart_getreg(bas, UART_CTRL);  in uart_mvebu_bus_ioctl()
418 		uart_setreg(bas, UART_CTRL, ctrl);  in uart_mvebu_bus_ioctl()
446 	ctrl = uart_getreg(bas, UART_CTRL);  in uart_mvebu_bus_ipend()
451 		uart_setreg(bas, UART_CTRL, ctrl & ~CTRL_TX_IDLE_INT);  in uart_mvebu_bus_ipend()
562 	ctrl = uart_getreg(bas, UART_CTRL);  in uart_mvebu_bus_transmit()
563 	uart_setreg(bas, UART_CTRL, ctrl & ~CTRL_INTR_MASK);  in uart_mvebu_bus_transmit()
575 	uart_setreg(bas, UART_CTRL, ctrl | CTRL_TX_IDLE_INT);  in uart_mvebu_bus_transmit()
594 	ctrl = uart_getreg(bas, UART_CTRL);  in uart_mvebu_bus_grab()
596 	uart_setreg(bas, UART_CTRL, ctrl & ~CTRL_INTR_MASK);  in uart_mvebu_bus_grab()
610 	ctrl = uart_getreg(bas, UART_CTRL) & ~CTRL_INTR_MASK;  in uart_mvebu_bus_ungrab()
611 	uart_setreg(bas, UART_CTRL, ctrl | msc->intrm);  in uart_mvebu_bus_ungrab()