169 #define WRITE_REG(sc,reg,val) \  macro
450 	WRITE_REG(sc, SAFE_HI_MASK, 0);		/* disable interrupts */  in safe_detach()
532 	WRITE_REG(sc, SAFE_HI_CLR, stat);	/* IACK */  in safe_intr()
617 	WRITE_REG(sc, SAFE_HI_RD_DESCR, 0);  in safe_feed()
1397 	WRITE_REG(sc, SAFE_RNG_CTRL, 0);  in safe_rng_init()
1399 	WRITE_REG(sc, SAFE_RNG_CNFG, 0x834);	/* magic from SafeNet */  in safe_rng_init()
1400 	WRITE_REG(sc, SAFE_RNG_ALM_CNT, 0);  in safe_rng_init()
1439 	WRITE_REG(sc, SAFE_RNG_CTRL,  in safe_rng_disable_short_cycle()
1446 	WRITE_REG(sc, SAFE_RNG_CTRL,   in safe_rng_enable_short_cycle()
1496 			WRITE_REG(sc, SAFE_RNG_CNFG, w);  in safe_rng()
1498 			WRITE_REG(sc, SAFE_RNG_ALM_CNT, 0);  in safe_rng()
1511 		WRITE_REG(sc, SAFE_RNG_ALM_CNT, 0);  in safe_rng()
1609 	WRITE_REG(sc, SAFE_PE_DMACFG, v  in safe_reset_board()
1613 	WRITE_REG(sc, SAFE_PE_DMACFG, v);  in safe_reset_board()
1633 	WRITE_REG(sc, SAFE_PE_DMACFG, v);  in safe_init_board()
1636 	WRITE_REG(sc, SAFE_ENDIAN, 0x1b);  in safe_init_board()
1646 		WRITE_REG(sc, SAFE_DMA_CFG, 256);  in safe_init_board()
1655 	WRITE_REG(sc, SAFE_PE_PDRBASE, sc->sc_ringalloc.dma_paddr);  in safe_init_board()
1656 	WRITE_REG(sc, SAFE_PE_RDRBASE, sc->sc_ringalloc.dma_paddr);  in safe_init_board()
1663 	WRITE_REG(sc, SAFE_PE_RINGCFG,  in safe_init_board()
1665 	WRITE_REG(sc, SAFE_PE_RINGPOLL, 0);	/* disable polling */  in safe_init_board()
1667 	WRITE_REG(sc, SAFE_PE_GRNGBASE, sc->sc_spalloc.dma_paddr);  in safe_init_board()
1668 	WRITE_REG(sc, SAFE_PE_SRNGBASE, sc->sc_dpalloc.dma_paddr);  in safe_init_board()
1669 	WRITE_REG(sc, SAFE_PE_PARTSIZE,  in safe_init_board()
1676 	WRITE_REG(sc, SAFE_PE_PARTCFG, SAFE_MAX_DSIZE);  in safe_init_board()
1679 	WRITE_REG(sc, SAFE_PE_DMACFG, v | SAFE_PE_DMACFG_PEMODE);  in safe_init_board()
1685 	WRITE_REG(sc, SAFE_HI_CFG, SAFE_HI_CFG_LEVEL);  in safe_init_board()
1686 	WRITE_REG(sc, SAFE_HI_DESC_CNT, 1);  in safe_init_board()
1687 	WRITE_REG(sc, SAFE_HI_MASK, SAFE_INT_PE_DDONE | SAFE_INT_PE_ERROR);  in safe_init_board()