166 #define	READ_REG(sc,r) \  macro
274 	sc->sc_chiprev = READ_REG(sc, SAFE_DEVINFO) &  in safe_attach()
377 	sc->sc_devinfo = READ_REG(sc, SAFE_DEVINFO);  in safe_attach()
528 	stat = READ_REG(sc, SAFE_HM_STAT);  in safe_intr()
574 			READ_REG(sc, SAFE_PE_DMASTAT)));  in safe_intr()
1416 	w = READ_REG(sc, SAFE_RNG_OUT);  in safe_rng_init()
1418 		v = READ_REG(sc, SAFE_RNG_OUT);  in safe_rng_init()
1429 		v = READ_REG(sc, SAFE_RNG_OUT);  in safe_rng_init()
1440 		READ_REG(sc, SAFE_RNG_CTRL) &~ SAFE_RNG_CTRL_SHORTEN);  in safe_rng_disable_short_cycle()
1447 		READ_REG(sc, SAFE_RNG_CTRL) | SAFE_RNG_CTRL_SHORTEN);  in safe_rng_enable_short_cycle()
1456 	while (READ_REG(sc, SAFE_RNG_STAT) != 0 && ++i < SAFE_RNG_MAXWAIT)  in safe_rng_read()
1458 	return READ_REG(sc, SAFE_RNG_OUT);  in safe_rng_read()
1484 	if (READ_REG(sc, SAFE_RNG_ALM_CNT) > safe_rngmaxalarm) {  in safe_rng()
1488 			READ_REG(sc, SAFE_RNG_ALM_CNT), safe_rngmaxalarm));  in safe_rng()
1493 			w = READ_REG(sc, SAFE_RNG_CNFG);  in safe_rng()
1503 			if (READ_REG(sc, SAFE_RNG_ALM_CNT) == 0) {  in safe_rng()
1606 	v = READ_REG(sc, SAFE_PE_DMACFG) &~  in safe_reset_board()
1624 	v = READ_REG(sc, SAFE_PE_DMACFG);  in safe_init_board()
1649 			(READ_REG(sc, SAFE_DMA_CFG)>>2) & 0xff,  in safe_init_board()
1808 		, READ_REG(sc, SAFE_DMA_ENDIAN)  in safe_dump_dmastatus()
1809 		, READ_REG(sc, SAFE_DMA_SRCADDR)  in safe_dump_dmastatus()
1810 		, READ_REG(sc, SAFE_DMA_DSTADDR)  in safe_dump_dmastatus()
1811 		, READ_REG(sc, SAFE_DMA_STAT)  in safe_dump_dmastatus()
1820 		, READ_REG(sc, SAFE_HI_CFG)  in safe_dump_intrstate()
1821 		, READ_REG(sc, SAFE_HI_MASK)  in safe_dump_intrstate()
1822 		, READ_REG(sc, SAFE_HI_DESC_CNT)  in safe_dump_intrstate()
1823 		, READ_REG(sc, SAFE_HU_STAT)  in safe_dump_intrstate()
1824 		, READ_REG(sc, SAFE_HM_STAT)  in safe_dump_intrstate()
1831 	u_int32_t estat = READ_REG(sc, SAFE_PE_ERNGSTAT);  in safe_dump_ringstate()