163 void		otus_write(struct otus_softc *, uint32_t, uint32_t);
1296 otus_write(struct otus_softc *sc, uint32_t reg, uint32_t val)  in otus_write()  function
2415 	otus_write(sc, AR_MAC_REG_GROUP_HASH_TBL_L, hashes[0]);  in otus_set_multi()
2416 	otus_write(sc, AR_MAC_REG_GROUP_HASH_TBL_H, hashes[1]);  in otus_set_multi()
2456 	otus_write(sc, AR_MAC_REG_AC0_CW,  in otus_updateedca_locked()
2459 	otus_write(sc, AR_MAC_REG_AC1_CW,  in otus_updateedca_locked()
2462 	otus_write(sc, AR_MAC_REG_AC2_CW,  in otus_updateedca_locked()
2465 	otus_write(sc, AR_MAC_REG_AC3_CW,  in otus_updateedca_locked()
2468 	otus_write(sc, AR_MAC_REG_AC4_CW,		/* Special TXQ. */  in otus_updateedca_locked()
2473 	otus_write(sc, AR_MAC_REG_AC1_AC0_AIFS,  in otus_updateedca_locked()
2477 	otus_write(sc, AR_MAC_REG_AC3_AC2_AIFS,  in otus_updateedca_locked()
2483 	otus_write(sc, AR_MAC_REG_AC1_AC0_TXOP,  in otus_updateedca_locked()
2486 	otus_write(sc, AR_MAC_REG_AC3_AC2_TXOP,  in otus_updateedca_locked()
2507 	otus_write(sc, AR_MAC_REG_SLOT_TIME, slottime << 10);  in otus_updateslot()
2534 	otus_write(sc, AR_MAC_REG_ACK_EXTENSION, 0x40);  in otus_init_mac()
2535 	otus_write(sc, AR_MAC_REG_RETRY_MAX, 0);  in otus_init_mac()
2536 	otus_write(sc, AR_MAC_REG_RX_THRESHOLD, 0xc1f80);  in otus_init_mac()
2537 	otus_write(sc, AR_MAC_REG_RX_PE_DELAY, 0x70);  in otus_init_mac()
2538 	otus_write(sc, AR_MAC_REG_EIFS_AND_SIFS, 0xa144000);  in otus_init_mac()
2539 	otus_write(sc, AR_MAC_REG_SLOT_TIME, 9 << 10);  in otus_init_mac()
2540 	otus_write(sc, AR_MAC_REG_TID_CFACK_CFEND_RATE, 0x19000000);  in otus_init_mac()
2542 	otus_write(sc, AR_MAC_REG_TXOP_DURATION, 0x201);  in otus_init_mac()
2544 	otus_write(sc, AR_MAC_REG_BCN_HT1, 0x8000170);  in otus_init_mac()
2545 	otus_write(sc, AR_MAC_REG_BACKOFF_PROTECT, 0x105);  in otus_init_mac()
2546 	otus_write(sc, AR_MAC_REG_AMPDU_FACTOR, 0x10000a);  in otus_init_mac()
2550 	otus_write(sc, AR_MAC_REG_BASIC_RATE, 0x150f);  in otus_init_mac()
2551 	otus_write(sc, AR_MAC_REG_MANDATORY_RATE, 0x150f);  in otus_init_mac()
2552 	otus_write(sc, AR_MAC_REG_RTS_CTS_RATE, 0x10b01bb);  in otus_init_mac()
2553 	otus_write(sc, AR_MAC_REG_ACK_TPC, 0x4003c1e);  in otus_init_mac()
2556 	otus_write(sc, AR_GPIO_REG_PORT_TYPE, 0x3);  in otus_init_mac()
2557 	otus_write(sc, AR_GPIO_REG_PORT_DATA, 0x3);  in otus_init_mac()
2559 	otus_write(sc, 0x1c3600, 0x3);  in otus_init_mac()
2560 	otus_write(sc, AR_MAC_REG_AMPDU_RX_THRESH, 0xffff);  in otus_init_mac()
2561 	otus_write(sc, AR_MAC_REG_MISC_680, 0xf00008);  in otus_init_mac()
2563 	otus_write(sc, AR_MAC_REG_RX_TIMEOUT, 0);  in otus_init_mac()
2566 	otus_write(sc, 0x1e1110, 0x4);  in otus_init_mac()
2568 	otus_write(sc, 0x1e1114, 0x80);  in otus_init_mac()
2571 	otus_write(sc, AR_PWR_REG_CLOCK_SEL, 0x73);  in otus_init_mac()
2573 	otus_write(sc, AR_MAC_REG_TXRX_MPI, 0x110011);  in otus_init_mac()
2574 	otus_write(sc, AR_MAC_REG_FCS_SELECT, 0x4);  in otus_init_mac()
2575 	otus_write(sc, AR_MAC_REG_TXOP_NOT_ENOUGH_INDICATION, 0x141e0f48);  in otus_init_mac()
2578 	otus_write(sc, AR_MAC_REG_ENCRYPTION, 0x78);  in otus_init_mac()
2622 	otus_write(sc, AR_PHY_SWITCH_COM, tmp);  in otus_set_board_values()
2625 	otus_write(sc, AR_PHY_SWITCH_CHAIN_0, tmp);  in otus_set_board_values()
2628 	otus_write(sc, AR_PHY_SWITCH_CHAIN_0 + offset, tmp);  in otus_set_board_values()
2634 		otus_write(sc, AR_PHY_SETTLING, tmp);  in otus_set_board_values()
2640 	otus_write(sc, AR_PHY_DESIRED_SZ, tmp);  in otus_set_board_values()
2644 	otus_write(sc, AR_PHY_RF_CTL4, tmp);  in otus_set_board_values()
2649 	otus_write(sc, AR_PHY_RF_CTL3, tmp);  in otus_set_board_values()
2654 	otus_write(sc, AR_PHY_CCA, tmp);  in otus_set_board_values()
2659 	otus_write(sc, AR_PHY_RXGAIN, tmp);  in otus_set_board_values()
2664 	otus_write(sc, AR_PHY_RXGAIN + offset, tmp);  in otus_set_board_values()
2673 	otus_write(sc, AR_PHY_GAIN_2GHZ, tmp);  in otus_set_board_values()
2678 	otus_write(sc, AR_PHY_GAIN_2GHZ + offset, tmp);  in otus_set_board_values()
2683 	otus_write(sc, AR_PHY_TIMING_CTRL4, tmp);  in otus_set_board_values()
2688 	otus_write(sc, AR_PHY_TIMING_CTRL4 + offset, tmp);  in otus_set_board_values()
2693 	otus_write(sc, AR_PHY_TPCRG1, tmp);  in otus_set_board_values()
2717 		otus_write(sc, AR_PHY(ar5416_phy_regs[i]), vals[i]);  in otus_program_phy()
2725 	otus_write(sc, AR_PHY_POWER_TX_RATE_MAX, 0x7f);  in otus_program_phy()
2726 	otus_write(sc, AR_PHY_POWER_TX_RATE1, 0x3f3f3f3f);  in otus_program_phy()
2727 	otus_write(sc, AR_PHY_POWER_TX_RATE2, 0x3f3f3f3f);  in otus_program_phy()
2728 	otus_write(sc, AR_PHY_POWER_TX_RATE3, 0x3f3f3f3f);  in otus_program_phy()
2729 	otus_write(sc, AR_PHY_POWER_TX_RATE4, 0x3f3f3f3f);  in otus_program_phy()
2730 	otus_write(sc, AR_PHY_POWER_TX_RATE5, 0x3f3f3f3f);  in otus_program_phy()
2731 	otus_write(sc, AR_PHY_POWER_TX_RATE6, 0x3f3f3f3f);  in otus_program_phy()
2732 	otus_write(sc, AR_PHY_POWER_TX_RATE7, 0x3f3f3f3f);  in otus_program_phy()
2733 	otus_write(sc, AR_PHY_POWER_TX_RATE8, 0x3f3f3f3f);  in otus_program_phy()
2734 	otus_write(sc, AR_PHY_POWER_TX_RATE9, 0x3f3f3f3f);  in otus_program_phy()
2737 		otus_write(sc, AR_PWR_REG_PLL_ADDAC, 0x5163);  in otus_program_phy()
2739 		otus_write(sc, AR_PWR_REG_PLL_ADDAC, 0x5143);  in otus_program_phy()
2783 	otus_write(sc, AR_PHY(44), data);  in otus_set_rf_bank4()
2786 	otus_write(sc, AR_PHY(58), data);  in otus_set_rf_bank4()
2832 	otus_write(sc, AR_MAC_REG_DYNAMIC_SIFS_ACK, tmp);  in otus_set_chan()
2837 	otus_write(sc, AR_PHY_HEAVY_CLIP_ENABLE, 0x200);  in otus_set_chan()
2851 		otus_write(sc, AR_PWR_REG_RESET, sc->bb_reset ? 0x800 : 0x400);  in otus_set_chan()
2854 		otus_write(sc, AR_PWR_REG_RESET, 0);  in otus_set_chan()
2872 			otus_write(sc, AR_PHY(ar5416_banks_regs[i]), vals[i]);  in otus_set_chan()
2888 	otus_write(sc, AR_PHY_TURBO, tmp);  in otus_set_chan()
3084 	otus_write(sc, AR_MAC_REG_BSSID_L,  in otus_set_bssid()
3086 	otus_write(sc, AR_MAC_REG_BSSID_H,  in otus_set_bssid()
3096 	otus_write(sc, AR_MAC_REG_MAC_ADDR_L,  in otus_set_macaddr()
3098 	otus_write(sc, AR_MAC_REG_MAC_ADDR_H,  in otus_set_macaddr()
3150 		otus_write(sc, AR_GPIO_REG_PORT_DATA, state);  in otus_led_newstate_type3()
3212 	otus_write(sc, AR_MAC_REG_SNIFFER, sniffer);  in otus_set_operating_mode()
3213 	otus_write(sc, AR_MAC_REG_CAM_MODE, cam_mode);  in otus_set_operating_mode()
3214 	otus_write(sc, AR_MAC_REG_ENCRYPTION, enc_mode);  in otus_set_operating_mode()
3215 	otus_write(sc, AR_MAC_REG_RX_CONTROL, rx_ctrl);  in otus_set_operating_mode()
3231 		otus_write(sc, AR_MAC_REG_FRAMETYPE_FILTER, 0xff00ffff);  in otus_set_rx_filter()
3235 		otus_write(sc, AR_MAC_REG_FRAMETYPE_FILTER, 0x0500ffff);  in otus_set_rx_filter()
3276 	otus_write(sc, AR_MAC_REG_DMA_TRIGGER, 0x100);  in otus_init()
3306 	otus_write(sc, AR_MAC_REG_DMA_TRIGGER, 0);  in otus_stop()