448 	if (hdr->command == SLI4_MBOX_COMMAND_SLI_CONFIG) {  in sli_dump_bmbx_command()
567 	config_link->hdr.command = SLI4_MBOX_COMMAND_CONFIG_LINK;  in sli_cmd_config_link()
591 	hdr->command = SLI4_MBOX_COMMAND_DOWN_LINK;  in sli_cmd_down_link()
616 	cmd->hdr.command = SLI4_MBOX_COMMAND_DUMP;  in sli_cmd_dump_type4()
696 	cmd->hdr.command = SLI4_MBOX_COMMAND_READ_LNK_STAT;  in sli_cmd_read_link_stats()
722 	cmd->hdr.command = SLI4_MBOX_COMMAND_READ_STATUS;  in sli_cmd_read_status()
842 	init_link->hdr.command = SLI4_MBOX_COMMAND_INIT_LINK;  in sli_cmd_init_link()
904 	init_vfi->hdr.command = SLI4_MBOX_COMMAND_INIT_VFI;  in sli_cmd_init_vfi()
940 	init_vpi->hdr.command = SLI4_MBOX_COMMAND_INIT_VPI;  in sli_cmd_init_vpi()
966 	post_xri->hdr.command = SLI4_MBOX_COMMAND_POST_XRI;  in sli_cmd_post_xri()
996 	release_xri->hdr.command = SLI4_MBOX_COMMAND_RELEASE_XRI;  in sli_cmd_release_xri()
1018 	read_config->hdr.command = SLI4_MBOX_COMMAND_READ_CONFIG;  in sli_cmd_read_config()
1039 	read_nvparms->hdr.command = SLI4_MBOX_COMMAND_READ_NVPARMS;  in sli_cmd_read_nvparms()
1065 	write_nvparms->hdr.command = SLI4_MBOX_COMMAND_WRITE_NVPARMS;  in sli_cmd_write_nvparms()
1091 	read_rev->hdr.command = SLI4_MBOX_COMMAND_READ_REV;  in sli_cmd_read_rev()
1135 	read_sparm64->hdr.command = SLI4_MBOX_COMMAND_READ_SPARM64;  in sli_cmd_read_sparm64()
1165 	read_topo->hdr.command = SLI4_MBOX_COMMAND_READ_TOPOLOGY;  in sli_cmd_read_topology()
1206 	reg_fcfi->hdr.command = SLI4_MBOX_COMMAND_REG_FCFI;  in sli_cmd_reg_fcfi()
1258 	reg_fcfi_mrq->hdr.command = SLI4_MBOX_COMMAND_REG_FCFI_MRQ;  in sli_cmd_reg_fcfi_mrq()
1314 	reg_rpi->hdr.command = SLI4_MBOX_COMMAND_REG_RPI;  in sli_cmd_reg_rpi()
1353 	reg_vfi->hdr.command = SLI4_MBOX_COMMAND_REG_VFI;  in sli_cmd_reg_vfi()
1400 	reg_vpi->hdr.command = SLI4_MBOX_COMMAND_REG_VPI;  in sli_cmd_reg_vpi()
1429 	features->hdr.command = SLI4_MBOX_COMMAND_REQUEST_FEATURES;  in sli_cmd_request_features()
1434 	features->command.dword = mask.dword;  in sli_cmd_request_features()
1466 	sli_config->hdr.command = SLI4_MBOX_COMMAND_SLI_CONFIG;  in sli_cmd_sli_config()
1545 	unreg_fcfi->hdr.command = SLI4_MBOX_COMMAND_UNREG_FCFI;  in sli_cmd_unreg_fcfi()
1578 	unreg_rpi->hdr.command = SLI4_MBOX_COMMAND_UNREG_RPI;  in sli_cmd_unreg_rpi()
1631 	unreg_vfi->hdr.command = SLI4_MBOX_COMMAND_UNREG_VFI;  in sli_cmd_unreg_vfi()
1676 	unreg_vpi->hdr.command = SLI4_MBOX_COMMAND_UNREG_VPI;  in sli_cmd_unreg_vpi()
1722 	req->hdr.command = SLI4_MBOX_COMMAND_CONFIG_AUTO_XFER_RDY;  in sli_cmd_config_auto_xfer_rdy()
1754         req->hdr.command = SLI4_MBOX_COMMAND_CONFIG_AUTO_XFER_RDY_HP;  in sli_cmd_config_auto_xfer_rdy_hp()
3285 	if (!buf || (SLI4_MBOX_COMMAND_SLI_CONFIG != sli_config->hdr.command)) {  in sli_res_sli_config()
3287 				buf ? sli_config->hdr.command : -1);  in sli_res_sli_config()
6571 	abort->command = SLI4_WQE_ABORT;  in sli_abort_wqe()
6636 	els->command = SLI4_WQE_ELS_REQUEST64;  in sli_els_request64_wqe()
6812 	icmnd->command = SLI4_WQE_FCP_ICMND64;  in sli_fcp_icmnd64_wqe()
6905 	iread->command = SLI4_WQE_FCP_IREAD64;  in sli_fcp_iread64_wqe()
7010 	iwrite->command = SLI4_WQE_FCP_IWRITE64;  in sli_fcp_iwrite64_wqe()
7130 	trecv->command = SLI4_WQE_FCP_TRECEIVE64;  in sli_fcp_treceive64_wqe()
7217 		trecv->command = SLI4_WQE_FCP_CONT_TRECEIVE64;  in sli_fcp_cont_treceive64_wqe()
7296 	trsp->command = SLI4_WQE_FCP_TRSP64;  in sli_fcp_trsp64_wqe()
7412 	tsend->command = SLI4_WQE_FCP_TSEND64;  in sli_fcp_tsend64_wqe()
7530 	gen->command = SLI4_WQE_GEN_REQUEST64;  in sli_gen_request64_wqe()
7599 	sf->command = SLI4_WQE_SEND_FRAME;  in sli_send_frame_wqe()
7692 	xmit->command = SLI4_WQE_XMIT_SEQUENCE64;  in sli_xmit_sequence64_wqe()
7737 	requeue->command = SLI4_WQE_REQUEUE_XRI;  in sli_requeue_xri_wqe()
7782 	bcast->command = SLI4_WQE_XMIT_BCAST64;  in sli_xmit_bcast64_wqe()
7872 	bls->command = SLI4_WQE_XMIT_BLS_RSP;  in sli_xmit_bls_rsp64_wqe()
7936 	els->command = SLI4_WQE_ELS_RSP64;  in sli_xmit_els_rsp64_wqe()