Lines Matching refs:dev_pgsz
270 U32 offset, entry_len, dev_pgsz; in mpi3mr_app_build_nvme_prp() local
294 dev_pgsz = 1 << (tgtdev->dev_spec.pcie_inf.pgsz); in mpi3mr_app_build_nvme_prp()
296 page_mask = dev_pgsz - 1; in mpi3mr_app_build_nvme_prp()
298 if (dev_pgsz > MPI3MR_IOCTL_SGE_SIZE){ in mpi3mr_app_build_nvme_prp()
300 __func__, dev_pgsz, MPI3MR_IOCTL_SGE_SIZE, dev_handle); in mpi3mr_app_build_nvme_prp()
304 if (MPI3MR_IOCTL_SGE_SIZE % dev_pgsz){ in mpi3mr_app_build_nvme_prp()
306 __func__, MPI3MR_IOCTL_SGE_SIZE, dev_pgsz, dev_handle); in mpi3mr_app_build_nvme_prp()
328 __func__, dma_addr, dev_pgsz); in mpi3mr_app_build_nvme_prp()
342 dev_pgsz, /* maxsize */ in mpi3mr_app_build_nvme_prp()
344 dev_pgsz, /* maxsegsize */ in mpi3mr_app_build_nvme_prp()
358 bzero(sc->nvme_encap_prp_list, dev_pgsz); in mpi3mr_app_build_nvme_prp()
360 sc->nvme_encap_prp_list, dev_pgsz, mpi3mr_memaddr_cb, &sc->nvme_encap_prp_list_dma, in mpi3mr_app_build_nvme_prp()
365 __func__, __LINE__, dev_pgsz); in mpi3mr_app_build_nvme_prp()
368 sc->nvme_encap_prp_sz = dev_pgsz; in mpi3mr_app_build_nvme_prp()
405 if (!page_mask_result && (length > dev_pgsz)) { in mpi3mr_app_build_nvme_prp()
412 entry_len = dev_pgsz - offset; in mpi3mr_app_build_nvme_prp()
438 if (length > dev_pgsz) { in mpi3mr_app_build_nvme_prp()