1026 #define MLX5_CAP_GEN(mdev, cap) \  argument
1027 	MLX5_GET(cmd_hca_cap, mdev->hca_caps_cur[MLX5_CAP_GENERAL], cap)
1029 #define	MLX5_CAP_GEN_64(mdev, cap)					\  argument
1030 	MLX5_GET64(cmd_hca_cap, mdev->hca_caps_cur[MLX5_CAP_GENERAL], cap)
1032 #define MLX5_CAP_GEN_MAX(mdev, cap) \  argument
1033 	MLX5_GET(cmd_hca_cap, mdev->hca_caps_max[MLX5_CAP_GENERAL], cap)
1035 #define MLX5_CAP_GEN_2(mdev, cap) \  argument
1036 	MLX5_GET(cmd_hca_cap_2, mdev->hca_caps_cur[MLX5_CAP_GENERAL_2], cap)
1038 #define MLX5_CAP_ETH(mdev, cap) \  argument
1040 		 mdev->hca_caps_cur[MLX5_CAP_ETHERNET_OFFLOADS], cap)
1042 #define MLX5_CAP_ETH_MAX(mdev, cap) \  argument
1044 		 mdev->hca_caps_max[MLX5_CAP_ETHERNET_OFFLOADS], cap)
1046 #define MLX5_CAP_ROCE(mdev, cap) \  argument
1047 	MLX5_GET(roce_cap, mdev->hca_caps_cur[MLX5_CAP_ROCE], cap)
1049 #define MLX5_CAP_ROCE_MAX(mdev, cap) \  argument
1050 	MLX5_GET(roce_cap, mdev->hca_caps_max[MLX5_CAP_ROCE], cap)
1052 #define MLX5_CAP_ATOMIC(mdev, cap) \  argument
1053 	MLX5_GET(atomic_caps, mdev->hca_caps_cur[MLX5_CAP_ATOMIC], cap)
1055 #define MLX5_CAP_ATOMIC_MAX(mdev, cap) \  argument
1056 	MLX5_GET(atomic_caps, mdev->hca_caps_max[MLX5_CAP_ATOMIC], cap)
1058 #define MLX5_CAP_FLOWTABLE(mdev, cap) \  argument
1059 	MLX5_GET(flow_table_nic_cap, mdev->hca_caps_cur[MLX5_CAP_FLOW_TABLE], cap)
1061 #define MLX5_CAP_FLOWTABLE_MAX(mdev, cap) \  argument
1062 	MLX5_GET(flow_table_nic_cap, mdev->hca_caps_max[MLX5_CAP_FLOW_TABLE], cap)
1064 #define MLX5_CAP_FLOWTABLE_NIC_RX(mdev, cap) \  argument
1065 	MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_receive.cap)
1067 #define MLX5_CAP_FLOWTABLE_NIC_RX_MAX(mdev, cap) \  argument
1068 	MLX5_CAP_FLOWTABLE_MAX(mdev, flow_table_properties_nic_receive.cap)
1070 #define MLX5_CAP_ESW_FLOWTABLE(mdev, cap) \  argument
1072 		 mdev->hca_caps_cur[MLX5_CAP_ESWITCH_FLOW_TABLE], cap)
1074 #define MLX5_CAP_ESW_FLOWTABLE_MAX(mdev, cap) \  argument
1076 		 mdev->hca_caps_max[MLX5_CAP_ESWITCH_FLOW_TABLE], cap)
1078 #define MLX5_CAP_ESW_FLOWTABLE_FDB(mdev, cap) \  argument
1079 	MLX5_CAP_ESW_FLOWTABLE(mdev, flow_table_properties_nic_esw_fdb.cap)
1081 #define MLX5_CAP_ESW_FLOWTABLE_FDB_MAX(mdev, cap) \  argument
1082 	MLX5_CAP_ESW_FLOWTABLE_MAX(mdev, flow_table_properties_nic_esw_fdb.cap)
1084 #define MLX5_CAP_ESW_EGRESS_ACL(mdev, cap) \  argument
1085 	MLX5_CAP_ESW_FLOWTABLE(mdev, flow_table_properties_esw_acl_egress.cap)
1087 #define MLX5_CAP_ESW_EGRESS_ACL_MAX(mdev, cap) \  argument
1088 	MLX5_CAP_ESW_FLOWTABLE_MAX(mdev, flow_table_properties_esw_acl_egress.cap)
1090 #define MLX5_CAP_ESW_INGRESS_ACL(mdev, cap) \  argument
1091 	MLX5_CAP_ESW_FLOWTABLE(mdev, flow_table_properties_esw_acl_ingress.cap)
1093 #define MLX5_CAP_ESW_INGRESS_ACL_MAX(mdev, cap) \  argument
1094 	MLX5_CAP_ESW_FLOWTABLE_MAX(mdev, flow_table_properties_esw_acl_ingress.cap)
1096 #define MLX5_CAP_ESW(mdev, cap) \  argument
1098 		 mdev->hca_caps_cur[MLX5_CAP_ESWITCH], cap)
1100 #define MLX5_CAP_ESW_MAX(mdev, cap) \  argument
1102 		 mdev->hca_caps_max[MLX5_CAP_ESWITCH], cap)
1104 #define MLX5_CAP_ODP(mdev, cap)\  argument
1105 	MLX5_GET(odp_cap, mdev->hca_caps_cur[MLX5_CAP_ODP], cap)
1107 #define MLX5_CAP_ODP_MAX(mdev, cap)\  argument
1108 	MLX5_GET(odp_cap, mdev->hca_caps_max[MLX5_CAP_ODP], cap)
1110 #define MLX5_CAP_SNAPSHOT(mdev, cap) \  argument
1112 		 mdev->hca_caps_cur[MLX5_CAP_SNAPSHOT], cap)
1114 #define MLX5_CAP_SNAPSHOT_MAX(mdev, cap) \  argument
1116 		 mdev->hca_caps_max[MLX5_CAP_SNAPSHOT], cap)
1118 #define MLX5_CAP_EOIB_OFFLOADS(mdev, cap) \  argument
1120 		 mdev->hca_caps_cur[MLX5_CAP_EOIB_OFFLOADS], cap)
1122 #define MLX5_CAP_EOIB_OFFLOADS_MAX(mdev, cap) \  argument
1124 		 mdev->hca_caps_max[MLX5_CAP_EOIB_OFFLOADS], cap)
1126 #define MLX5_CAP_DEBUG(mdev, cap) \  argument
1128 		 mdev->hca_caps_cur[MLX5_CAP_DEBUG], cap)
1130 #define MLX5_CAP_DEBUG_MAX(mdev, cap) \  argument
1132 		 mdev->hca_caps_max[MLX5_CAP_DEBUG], cap)
1134 #define MLX5_CAP_QOS(mdev, cap) \  argument
1136 		 mdev->hca_caps_cur[MLX5_CAP_QOS], cap)
1138 #define MLX5_CAP_QOS_MAX(mdev, cap) \  argument
1140 		 mdev->hca_caps_max[MLX5_CAP_QOS], cap)
1142 #define MLX5_CAP_PCAM_FEATURE(mdev, fld) \  argument
1143 	MLX5_GET(pcam_reg, (mdev)->caps.pcam, feature_cap_mask.enhanced_features.fld)
1145 #define	MLX5_CAP_PCAM_REG(mdev, reg) \  argument
1146 	MLX5_GET(pcam_reg, (mdev)->caps.pcam, port_access_reg_cap_mask.regs_5000_to_507f.reg)
1148 #define MLX5_CAP_MCAM_FEATURE(mdev, fld) \  argument
1149 	MLX5_GET(mcam_reg, (mdev)->caps.mcam, mng_feature_cap_mask.enhanced_features.fld)
1151 #define	MLX5_CAP_MCAM_REG(mdev, reg) \  argument
1152 	MLX5_GET(mcam_reg, (mdev)->caps.mcam, mng_access_reg_cap_mask.access_regs.reg)
1154 #define	MLX5_CAP_QCAM_REG(mdev, fld) \  argument
1155 	MLX5_GET(qcam_reg, (mdev)->caps.qcam, qos_access_reg_cap_mask.reg_cap.fld)
1157 #define	MLX5_CAP_QCAM_FEATURE(mdev, fld) \  argument
1158 	MLX5_GET(qcam_reg, (mdev)->caps.qcam, qos_feature_cap_mask.feature_cap.fld)
1160 #define MLX5_CAP_FPGA(mdev, cap) \  argument
1161 	MLX5_GET(fpga_cap, (mdev)->caps.fpga, cap)
1163 #define MLX5_CAP64_FPGA(mdev, cap) \  argument
1164 	MLX5_GET64(fpga_cap, (mdev)->caps.fpga, cap)
1166 #define	MLX5_CAP_TLS(mdev, cap) \  argument
1167 	MLX5_GET(tls_capabilities, (mdev)->hca_caps_cur[MLX5_CAP_TLS], cap)
1169 #define	MLX5_CAP_DEV_EVENT(mdev, cap)\  argument
1170 	MLX5_ADDR_OF(device_event_cap, (mdev)->hca_caps_cur[MLX5_CAP_DEV_EVENT], cap)