Lines Matching refs:priv
34 gve_reg_bar_read_4(struct gve_priv *priv, bus_size_t offset) in gve_reg_bar_read_4() argument
36 return (be32toh(bus_read_4(priv->reg_bar, offset))); in gve_reg_bar_read_4()
40 gve_reg_bar_write_4(struct gve_priv *priv, bus_size_t offset, uint32_t val) in gve_reg_bar_write_4() argument
42 bus_write_4(priv->reg_bar, offset, htobe32(val)); in gve_reg_bar_write_4()
46 gve_db_bar_write_4(struct gve_priv *priv, bus_size_t offset, uint32_t val) in gve_db_bar_write_4() argument
48 bus_write_4(priv->db_bar, offset, htobe32(val)); in gve_db_bar_write_4()
79 gve_dma_alloc_coherent(struct gve_priv *priv, int size, int align, in gve_dma_alloc_coherent() argument
83 device_t dev = priv->dev; in gve_dma_alloc_coherent()
144 gve_dmamap_create(struct gve_priv *priv, int size, int align, in gve_dmamap_create() argument
148 device_t dev = priv->dev; in gve_dmamap_create()
210 struct gve_priv *priv = arg; in gve_mgmnt_intr() local
212 taskqueue_enqueue(priv->service_tq, &priv->service_task); in gve_mgmnt_intr()
217 gve_free_irqs(struct gve_priv *priv) in gve_free_irqs() argument
225 if (priv->irq_tbl == NULL) { in gve_free_irqs()
226 device_printf(priv->dev, "No irq table, nothing to free\n"); in gve_free_irqs()
230 num_irqs = priv->tx_cfg.num_queues + priv->rx_cfg.num_queues + 1; in gve_free_irqs()
233 irq = &priv->irq_tbl[i]; in gve_free_irqs()
239 rc = bus_teardown_intr(priv->dev, irq->res, irq->cookie); in gve_free_irqs()
241 device_printf(priv->dev, "Failed to teardown irq num %d\n", in gve_free_irqs()
244 rc = bus_release_resource(priv->dev, SYS_RES_IRQ, in gve_free_irqs()
247 device_printf(priv->dev, "Failed to release irq num %d\n", in gve_free_irqs()
254 free(priv->irq_tbl, M_GVE); in gve_free_irqs()
255 priv->irq_tbl = NULL; in gve_free_irqs()
258 pci_release_msi(priv->dev); in gve_free_irqs()
262 gve_alloc_irqs(struct gve_priv *priv) in gve_alloc_irqs() argument
264 int num_tx = priv->tx_cfg.num_queues; in gve_alloc_irqs()
265 int num_rx = priv->rx_cfg.num_queues; in gve_alloc_irqs()
277 if (pci_alloc_msix(priv->dev, &got_nvecs) != 0) { in gve_alloc_irqs()
278 device_printf(priv->dev, "Failed to acquire any msix vectors\n"); in gve_alloc_irqs()
282 device_printf(priv->dev, "Tried to acquire %d msix vectors, got only %d\n", in gve_alloc_irqs()
289 device_printf(priv->dev, "Enabled MSIX with %d vectors\n", got_nvecs); in gve_alloc_irqs()
291 priv->irq_tbl = malloc(sizeof(struct gve_irq) * req_nvecs, M_GVE, in gve_alloc_irqs()
295 irq = &priv->irq_tbl[i]; in gve_alloc_irqs()
296 tx = &priv->tx[i]; in gve_alloc_irqs()
300 irq->res = bus_alloc_resource_any(priv->dev, SYS_RES_IRQ, in gve_alloc_irqs()
303 device_printf(priv->dev, "Failed to alloc irq %d for Tx queue %d\n", in gve_alloc_irqs()
309 err = bus_setup_intr(priv->dev, irq->res, INTR_TYPE_NET | INTR_MPSAFE, in gve_alloc_irqs()
310 gve_tx_intr, NULL, &priv->tx[i], &irq->cookie); in gve_alloc_irqs()
312 device_printf(priv->dev, "Failed to setup irq %d for Tx queue %d, " in gve_alloc_irqs()
317 bus_describe_intr(priv->dev, irq->res, irq->cookie, "tx%d", i); in gve_alloc_irqs()
322 irq = &priv->irq_tbl[i + j]; in gve_alloc_irqs()
323 rx = &priv->rx[j]; in gve_alloc_irqs()
327 irq->res = bus_alloc_resource_any(priv->dev, SYS_RES_IRQ, in gve_alloc_irqs()
330 device_printf(priv->dev, in gve_alloc_irqs()
336 err = bus_setup_intr(priv->dev, irq->res, INTR_TYPE_NET | INTR_MPSAFE, in gve_alloc_irqs()
337 gve_rx_intr, NULL, &priv->rx[j], &irq->cookie); in gve_alloc_irqs()
339 device_printf(priv->dev, "Failed to setup irq %d for Rx queue %d, " in gve_alloc_irqs()
344 bus_describe_intr(priv->dev, irq->res, irq->cookie, "rx%d", j); in gve_alloc_irqs()
350 irq = &priv->irq_tbl[m]; in gve_alloc_irqs()
352 irq->res = bus_alloc_resource_any(priv->dev, SYS_RES_IRQ, in gve_alloc_irqs()
355 device_printf(priv->dev, "Failed to allocate irq %d for mgmnt queue\n", rid); in gve_alloc_irqs()
360 err = bus_setup_intr(priv->dev, irq->res, INTR_TYPE_NET | INTR_MPSAFE, in gve_alloc_irqs()
361 gve_mgmnt_intr, NULL, priv, &irq->cookie); in gve_alloc_irqs()
363 device_printf(priv->dev, "Failed to setup irq %d for mgmnt queue, err: %d\n", in gve_alloc_irqs()
368 bus_describe_intr(priv->dev, irq->res, irq->cookie, "mgmnt"); in gve_alloc_irqs()
373 gve_free_irqs(priv); in gve_alloc_irqs()
378 gve_unmask_all_queue_irqs(struct gve_priv *priv) in gve_unmask_all_queue_irqs() argument
384 for (idx = 0; idx < priv->tx_cfg.num_queues; idx++) { in gve_unmask_all_queue_irqs()
385 tx = &priv->tx[idx]; in gve_unmask_all_queue_irqs()
386 gve_db_bar_write_4(priv, tx->com.irq_db_offset, 0); in gve_unmask_all_queue_irqs()
388 for (idx = 0; idx < priv->rx_cfg.num_queues; idx++) { in gve_unmask_all_queue_irqs()
389 rx = &priv->rx[idx]; in gve_unmask_all_queue_irqs()
390 gve_db_bar_write_4(priv, rx->com.irq_db_offset, 0); in gve_unmask_all_queue_irqs()
395 gve_mask_all_queue_irqs(struct gve_priv *priv) in gve_mask_all_queue_irqs() argument
397 for (int idx = 0; idx < priv->tx_cfg.num_queues; idx++) { in gve_mask_all_queue_irqs()
398 struct gve_tx_ring *tx = &priv->tx[idx]; in gve_mask_all_queue_irqs()
399 gve_db_bar_write_4(priv, tx->com.irq_db_offset, GVE_IRQ_MASK); in gve_mask_all_queue_irqs()
401 for (int idx = 0; idx < priv->rx_cfg.num_queues; idx++) { in gve_mask_all_queue_irqs()
402 struct gve_rx_ring *rx = &priv->rx[idx]; in gve_mask_all_queue_irqs()
403 gve_db_bar_write_4(priv, rx->com.irq_db_offset, GVE_IRQ_MASK); in gve_mask_all_queue_irqs()