Lines Matching refs:REG_PORT

274 	sc->swid = e6000sw_readreg(sc, REG_PORT(sc, 0), SWITCH_ID) & 0xfff0;  in e6000sw_probe()
581 			reg = e6000sw_readreg(sc, REG_PORT(sc, port),
585 			e6000sw_writereg(sc, REG_PORT(sc, port), PSC_CONTROL,
611 			e6000sw_writereg(sc, REG_PORT(sc, port), PSC_CONTROL,
950 	reg = e6000sw_readreg(sc, REG_PORT(sc, p->es_port), PORT_CONTROL2);
999 	reg = e6000sw_readreg(sc, REG_PORT(sc, p->es_port), PORT_CONTROL2);
1008 	e6000sw_writereg(sc, REG_PORT(sc, p->es_port), PORT_CONTROL2, reg);
1029 	reg = e6000sw_readreg(sc, REG_PORT(sc, port), PORT_VLAN_MAP);
1033 	e6000sw_writereg(sc, REG_PORT(sc, port), PORT_VLAN_MAP, reg);
1034 	reg = e6000sw_readreg(sc, REG_PORT(sc, port), PORT_CONTROL1);
1037 	e6000sw_writereg(sc, REG_PORT(sc, port), PORT_CONTROL1, reg);
1048 		ret = e6000sw_readreg(sc, REG_PORT(sc, port), PORT_CONTROL);
1049 		e6000sw_writereg(sc, REG_PORT(sc, port), PORT_CONTROL,
1058 		ret = e6000sw_readreg(sc, REG_PORT(sc, port), PORT_CONTROL);
1060 		e6000sw_writereg(sc, REG_PORT(sc, port), PORT_CONTROL, ret);
1063 		ret = e6000sw_readreg(sc, REG_PORT(sc, port), PORT_CONTROL2);
1067 		e6000sw_writereg(sc, REG_PORT(sc, port), PORT_CONTROL2, ret);
1074 		ret = e6000sw_readreg(sc, REG_PORT(sc, port), PORT_VID);
1085 		e6000sw_writereg(sc, REG_PORT(sc, port), PORT_VID, ret);
1116 		ret = e6000sw_readreg(sc, REG_PORT(sc, port), PORT_CONTROL);
1117 		e6000sw_writereg(sc, REG_PORT(sc, port), PORT_CONTROL,
1158 	    (addr_reg < (REG_PORT(sc, 0) * 32))) {
1174 	    (addr_reg < (REG_PORT(sc, 0) * 32))) {
1298 	reg = e6000sw_readreg(sc, REG_PORT(sc, port), PORT_VLAN_MAP);
1302 	reg = e6000sw_readreg(sc, REG_PORT(sc, port), PORT_CONTROL1);
1517 	reg = e6000sw_readreg(sc, REG_PORT(sc, port), PORT_VID);
1520 	e6000sw_writereg(sc, REG_PORT(sc, port), PORT_VID, reg);
1530 	*pvid = e6000sw_readreg(sc, REG_PORT(sc, port), PORT_VID) &
1594 		portstatus = e6000sw_readreg(sc, REG_PORT(sc, port),