Lines Matching refs:CSR_WRITE_4
309 CSR_WRITE_4(sc, ET_PM, pmcfg); in et_attach()
420 CSR_WRITE_4(sc, ET_MII_CMD, 0); in et_miibus_readreg()
424 CSR_WRITE_4(sc, ET_MII_ADDR, val); in et_miibus_readreg()
427 CSR_WRITE_4(sc, ET_MII_CMD, ET_MII_CMD_READ); in et_miibus_readreg()
451 CSR_WRITE_4(sc, ET_MII_CMD, 0); in et_miibus_readreg()
464 CSR_WRITE_4(sc, ET_MII_CMD, 0); in et_miibus_writereg()
468 CSR_WRITE_4(sc, ET_MII_ADDR, val); in et_miibus_writereg()
471 CSR_WRITE_4(sc, ET_MII_CTRL, in et_miibus_writereg()
491 CSR_WRITE_4(sc, ET_MII_CMD, 0); in et_miibus_writereg()
573 CSR_WRITE_4(sc, ET_MAC_CTRL, ctrl); in et_miibus_statchg()
574 CSR_WRITE_4(sc, ET_MAC_CFG2, cfg2); in et_miibus_statchg()
576 CSR_WRITE_4(sc, ET_MAC_CFG1, cfg1); in et_miibus_statchg()
652 CSR_WRITE_4(sc, ET_INTR_MASK, 0xffffffff); in et_stop()
654 CSR_WRITE_4(sc, ET_MAC_CFG1, CSR_READ_4(sc, ET_MAC_CFG1) & ~( in et_stop()
766 CSR_WRITE_4(sc, ET_MAC_CFG1, in et_reset()
771 CSR_WRITE_4(sc, ET_SWRST, in et_reset()
776 CSR_WRITE_4(sc, ET_MAC_CFG1, in et_reset()
779 CSR_WRITE_4(sc, ET_MAC_CFG1, 0); in et_reset()
781 CSR_WRITE_4(sc, ET_INTR_MASK, 0xffffffff); in et_reset()
1138 CSR_WRITE_4(sc, ET_LOOPBACK, 0); in et_chip_attach()
1141 CSR_WRITE_4(sc, ET_MAC_CFG1, in et_chip_attach()
1153 CSR_WRITE_4(sc, ET_MAC_HDX, val); in et_chip_attach()
1156 CSR_WRITE_4(sc, ET_MAC_CTRL, 0); in et_chip_attach()
1159 CSR_WRITE_4(sc, ET_MII_CFG, ET_MII_CFG_CLKRST); in et_chip_attach()
1162 CSR_WRITE_4(sc, ET_MAC_CFG1, 0); in et_chip_attach()
1165 CSR_WRITE_4(sc, ET_MMC_CTRL, ET_MMC_CTRL_ENABLE); in et_chip_attach()
1186 CSR_WRITE_4(sc, ET_INTR_MASK, 0xffffffff); in et_intr()
1201 CSR_WRITE_4(sc, ET_TIMER, sc->sc_timer); in et_intr()
1203 CSR_WRITE_4(sc, ET_INTR_MASK, ~ET_INTRS); in et_intr()
1247 CSR_WRITE_4(sc, ET_INTR_MASK, ~ET_INTRS); in et_init_locked()
1249 CSR_WRITE_4(sc, ET_TIMER, sc->sc_timer); in et_init_locked()
1430 CSR_WRITE_4(sc, ET_TX_READY_POS, tx_ready_pos); in et_start_locked()
1472 CSR_WRITE_4(sc, ET_RXDMA_CTRL, in et_stop_rxdma()
1487 CSR_WRITE_4(sc, ET_TXDMA_CTRL, in et_stop_txdma()
1596 CSR_WRITE_4(sc, ET_MULTI_HASH + (i * 4), hash[i]); in et_setmulti()
1602 CSR_WRITE_4(sc, ET_PKTFILT, pktfilt); in et_setmulti()
1603 CSR_WRITE_4(sc, ET_RXMAC_CTRL, rxmac_ctrl); in et_setmulti()
1629 CSR_WRITE_4(sc, ET_RXQUEUE_START, ET_QUEUE_ADDR_START); in et_chip_init()
1630 CSR_WRITE_4(sc, ET_RXQUEUE_END, rxq_end); in et_chip_init()
1631 CSR_WRITE_4(sc, ET_TXQUEUE_START, rxq_end + 1); in et_chip_init()
1632 CSR_WRITE_4(sc, ET_TXQUEUE_END, ET_QUEUE_ADDR_END); in et_chip_init()
1635 CSR_WRITE_4(sc, ET_LOOPBACK, 0); in et_chip_init()
1639 CSR_WRITE_4(sc, ET_MSI_CFG, 0); in et_chip_init()
1642 CSR_WRITE_4(sc, ET_TIMER, 0); in et_chip_init()
1648 CSR_WRITE_4(sc, ET_MMC_CTRL, ET_MMC_CTRL_ENABLE); in et_chip_init()
1743 CSR_WRITE_4(sc, ET_RX_STATUS_HI, ET_ADDR_HI(rxsd->rxsd_paddr)); in et_init_rxdma()
1744 CSR_WRITE_4(sc, ET_RX_STATUS_LO, ET_ADDR_LO(rxsd->rxsd_paddr)); in et_init_rxdma()
1750 CSR_WRITE_4(sc, ET_RXSTAT_HI, ET_ADDR_HI(rxst_ring->rsr_paddr)); in et_init_rxdma()
1751 CSR_WRITE_4(sc, ET_RXSTAT_LO, ET_ADDR_LO(rxst_ring->rsr_paddr)); in et_init_rxdma()
1752 CSR_WRITE_4(sc, ET_RXSTAT_CNT, ET_RX_NSTAT - 1); in et_init_rxdma()
1753 CSR_WRITE_4(sc, ET_RXSTAT_POS, 0); in et_init_rxdma()
1754 CSR_WRITE_4(sc, ET_RXSTAT_MINCNT, ((ET_RX_NSTAT * 15) / 100) - 1); in et_init_rxdma()
1764 CSR_WRITE_4(sc, ET_RX_RING1_HI, ET_ADDR_HI(rx_ring->rr_paddr)); in et_init_rxdma()
1765 CSR_WRITE_4(sc, ET_RX_RING1_LO, ET_ADDR_LO(rx_ring->rr_paddr)); in et_init_rxdma()
1766 CSR_WRITE_4(sc, ET_RX_RING1_CNT, ET_RX_NDESC - 1); in et_init_rxdma()
1767 CSR_WRITE_4(sc, ET_RX_RING1_POS, ET_RX_RING1_POS_WRAP); in et_init_rxdma()
1768 CSR_WRITE_4(sc, ET_RX_RING1_MINCNT, ((ET_RX_NDESC * 15) / 100) - 1); in et_init_rxdma()
1778 CSR_WRITE_4(sc, ET_RX_RING0_HI, ET_ADDR_HI(rx_ring->rr_paddr)); in et_init_rxdma()
1779 CSR_WRITE_4(sc, ET_RX_RING0_LO, ET_ADDR_LO(rx_ring->rr_paddr)); in et_init_rxdma()
1780 CSR_WRITE_4(sc, ET_RX_RING0_CNT, ET_RX_NDESC - 1); in et_init_rxdma()
1781 CSR_WRITE_4(sc, ET_RX_RING0_POS, ET_RX_RING0_POS_WRAP); in et_init_rxdma()
1782 CSR_WRITE_4(sc, ET_RX_RING0_MINCNT, ((ET_RX_NDESC * 15) / 100) - 1); in et_init_rxdma()
1791 CSR_WRITE_4(sc, ET_RX_INTR_NPKTS, sc->sc_rx_intr_npkts); in et_init_rxdma()
1792 CSR_WRITE_4(sc, ET_RX_INTR_DELAY, sc->sc_rx_intr_delay); in et_init_rxdma()
1814 CSR_WRITE_4(sc, ET_TX_RING_HI, ET_ADDR_HI(tx_ring->tr_paddr)); in et_init_txdma()
1815 CSR_WRITE_4(sc, ET_TX_RING_LO, ET_ADDR_LO(tx_ring->tr_paddr)); in et_init_txdma()
1816 CSR_WRITE_4(sc, ET_TX_RING_CNT, ET_TX_NDESC - 1); in et_init_txdma()
1822 CSR_WRITE_4(sc, ET_TX_STATUS_HI, ET_ADDR_HI(txsd->txsd_paddr)); in et_init_txdma()
1823 CSR_WRITE_4(sc, ET_TX_STATUS_LO, ET_ADDR_LO(txsd->txsd_paddr)); in et_init_txdma()
1825 CSR_WRITE_4(sc, ET_TX_READY_POS, 0); in et_init_txdma()
1842 CSR_WRITE_4(sc, ET_MAC_CFG1, in et_init_mac()
1854 CSR_WRITE_4(sc, ET_IPG, val); in et_init_mac()
1863 CSR_WRITE_4(sc, ET_MAC_HDX, val); in et_init_mac()
1866 CSR_WRITE_4(sc, ET_MAC_CTRL, 0); in et_init_mac()
1869 CSR_WRITE_4(sc, ET_MII_CFG, ET_MII_CFG_CLKRST); in et_init_mac()
1877 CSR_WRITE_4(sc, ET_MAC_ADDR1, val); in et_init_mac()
1879 CSR_WRITE_4(sc, ET_MAC_ADDR2, val); in et_init_mac()
1882 CSR_WRITE_4(sc, ET_MAX_FRMLEN, ET_FRAMELEN(if_getmtu(ifp))); in et_init_mac()
1885 CSR_WRITE_4(sc, ET_MAC_CFG1, 0); in et_init_mac()
1897 CSR_WRITE_4(sc, ET_RXMAC_CTRL, ET_RXMAC_CTRL_WOL_DISABLE); in et_init_rxmac()
1903 CSR_WRITE_4(sc, ET_WOL_CRC + (i * 4), 0); in et_init_rxmac()
1905 CSR_WRITE_4(sc, ET_WOL_MASK + (i * 4), 0); in et_init_rxmac()
1913 CSR_WRITE_4(sc, ET_WOL_SA_LO, val); in et_init_rxmac()
1915 CSR_WRITE_4(sc, ET_WOL_SA_HI, val); in et_init_rxmac()
1918 CSR_WRITE_4(sc, ET_PKTFILT, 0); in et_init_rxmac()
1921 CSR_WRITE_4(sc, ET_UCAST_FILTADDR1, 0); in et_init_rxmac()
1922 CSR_WRITE_4(sc, ET_UCAST_FILTADDR2, 0); in et_init_rxmac()
1923 CSR_WRITE_4(sc, ET_UCAST_FILTADDR3, 0); in et_init_rxmac()
1942 CSR_WRITE_4(sc, ET_RXMAC_MC_SEGSZ, val); in et_init_rxmac()
1944 CSR_WRITE_4(sc, ET_RXMAC_MC_WATERMARK, 0); in et_init_rxmac()
1947 CSR_WRITE_4(sc, ET_RXMAC_MGT, 0); in et_init_rxmac()
1949 CSR_WRITE_4(sc, ET_RXMAC_SPACE_AVL, 0); in et_init_rxmac()
1951 CSR_WRITE_4(sc, ET_RXMAC_MGT, in et_init_rxmac()
1963 CSR_WRITE_4(sc, ET_PKTFILT, val); in et_init_rxmac()
1966 CSR_WRITE_4(sc, ET_RXMAC_CTRL, in et_init_rxmac()
1980 CSR_WRITE_4(sc, ET_TXMAC_CTRL, ET_TXMAC_CTRL_FC_DISABLE); in et_init_txmac()
1987 CSR_WRITE_4(sc, ET_TXMAC_FLOWCTRL, 0 << ET_TXMAC_FLOWCTRL_CFPT_SHIFT); in et_init_txmac()
1990 CSR_WRITE_4(sc, ET_TXMAC_CTRL, in et_init_txmac()
2004 CSR_WRITE_4(sc, ET_RXDMA_CTRL, val); in et_start_rxdma()
2019 CSR_WRITE_4(sc, ET_TXDMA_CTRL, ET_TXDMA_CTRL_SINGLE_EPKT); in et_start_txdma()
2081 CSR_WRITE_4(sc, ET_RXSTAT_POS, rxstat_pos); in et_rxeof()
2132 CSR_WRITE_4(sc, rx_ring->rr_posreg, rxring_pos); in et_rxeof()
2578 CSR_WRITE_4(sc, ET_RX_INTR_NPKTS, v); in et_sysctl_rx_intr_npkts()
2605 CSR_WRITE_4(sc, ET_RX_INTR_DELAY, v); in et_sysctl_rx_intr_delay()
2710 CSR_WRITE_4(sc, ET_PM, pmcfg); in et_suspend()
2727 CSR_WRITE_4(sc, ET_PM, pmcfg); in et_resume()