757 typedef elink_status_t (*read_sfp_module_eeprom_func_p)(struct elink_phy *phy,
948 static elink_status_t elink_sfp_module_detection(struct elink_phy *phy,
2250 				   params->phy[phy_index].mdio_ctrl);  in elink_set_mdio_emac_per_phy()
2543 	if (!(params->phy[ELINK_INT_PHY].flags & ELINK_FLAGS_TX_ERROR_CHECK)) {  in elink_xmac_enable()
2574 	    (params->phy[ELINK_INT_PHY].supported &  in elink_xmac_enable()
3413 				       struct elink_phy *phy,  in elink_cl22_write()  argument
3420 	mode = REG_RD(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE);  in elink_cl22_write()
3421 	REG_WR(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE,  in elink_cl22_write()
3425 	tmp = ((phy->addr << 21) | (reg << 16) | val |  in elink_cl22_write()
3428 	REG_WR(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp);  in elink_cl22_write()
3433 		tmp = REG_RD(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);  in elink_cl22_write()
3443 	REG_WR(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, mode);  in elink_cl22_write()
3448 				      struct elink_phy *phy,  in elink_cl22_read()  argument
3456 	mode = REG_RD(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE);  in elink_cl22_read()
3457 	REG_WR(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE,  in elink_cl22_read()
3461 	val = ((phy->addr << 21) | (reg << 16) |  in elink_cl22_read()
3464 	REG_WR(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val);  in elink_cl22_read()
3469 		val = REG_RD(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);  in elink_cl22_read()
3482 	REG_WR(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, mode);  in elink_cl22_read()
3489 static elink_status_t elink_cl45_read(struct bxe_softc *sc, struct elink_phy *phy,  in elink_cl45_read()  argument
3496 	if (phy->flags & ELINK_FLAGS_MDC_MDIO_WA_G) {  in elink_cl45_read()
3499 		elink_set_mdio_clk(sc, chip_id, phy->mdio_ctrl);  in elink_cl45_read()
3502 	if (phy->flags & ELINK_FLAGS_MDC_MDIO_WA_B0)  in elink_cl45_read()
3503 		elink_bits_en(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS,  in elink_cl45_read()
3506 	val = ((phy->addr << 21) | (devad << 16) | reg |  in elink_cl45_read()
3509 	REG_WR(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val);  in elink_cl45_read()
3514 		val = REG_RD(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);  in elink_cl45_read()
3528 		val = ((phy->addr << 21) | (devad << 16) |  in elink_cl45_read()
3531 		REG_WR(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val);  in elink_cl45_read()
3536 			val = REG_RD(sc, phy->mdio_ctrl +  in elink_cl45_read()
3552 	if (phy->flags & ELINK_FLAGS_MDC_MDIO_WA) {  in elink_cl45_read()
3553 		phy->flags ^= ELINK_FLAGS_DUMMY_READ;  in elink_cl45_read()
3554 		if (phy->flags & ELINK_FLAGS_DUMMY_READ) {  in elink_cl45_read()
3556 			elink_cl45_read(sc, phy, devad, 0xf, &temp_val);  in elink_cl45_read()
3560 	if (phy->flags & ELINK_FLAGS_MDC_MDIO_WA_B0)  in elink_cl45_read()
3561 		elink_bits_dis(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS,  in elink_cl45_read()
3566 static elink_status_t elink_cl45_write(struct bxe_softc *sc, struct elink_phy *phy,  in elink_cl45_write()  argument
3573 	if (phy->flags & ELINK_FLAGS_MDC_MDIO_WA_G) {  in elink_cl45_write()
3576 		elink_set_mdio_clk(sc, chip_id, phy->mdio_ctrl);  in elink_cl45_write()
3579 	if (phy->flags & ELINK_FLAGS_MDC_MDIO_WA_B0)  in elink_cl45_write()
3580 		elink_bits_en(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS,  in elink_cl45_write()
3584 	tmp = ((phy->addr << 21) | (devad << 16) | reg |  in elink_cl45_write()
3587 	REG_WR(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp);  in elink_cl45_write()
3592 		tmp = REG_RD(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);  in elink_cl45_write()
3605 		tmp = ((phy->addr << 21) | (devad << 16) | val |  in elink_cl45_write()
3608 		REG_WR(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp);  in elink_cl45_write()
3613 			tmp = REG_RD(sc, phy->mdio_ctrl +  in elink_cl45_write()
3628 	if (phy->flags & ELINK_FLAGS_MDC_MDIO_WA) {  in elink_cl45_write()
3629 		phy->flags ^= ELINK_FLAGS_DUMMY_READ;  in elink_cl45_write()
3630 		if (phy->flags & ELINK_FLAGS_DUMMY_READ) {  in elink_cl45_write()
3632 			elink_cl45_read(sc, phy, devad, 0xf, &temp_val);  in elink_cl45_write()
3635 	if (phy->flags & ELINK_FLAGS_MDC_MDIO_WA_B0)  in elink_cl45_write()
3636 		elink_bits_dis(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS,  in elink_cl45_write()
3779 static elink_status_t elink_eee_disable(struct elink_phy *phy,  in elink_eee_disable()  argument
3788 	elink_cl45_write(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_EEE_ADV, 0x0);  in elink_eee_disable()
3795 static elink_status_t elink_eee_advertise(struct elink_phy *phy,  in elink_eee_advertise()  argument
3814 	elink_cl45_write(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_EEE_ADV, val);  in elink_eee_advertise()
3832 static void elink_eee_an_resolve(struct elink_phy *phy,  in elink_eee_an_resolve()  argument
3841 	elink_cl45_read(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_EEE_ADV, &adv);  in elink_eee_an_resolve()
3842 	elink_cl45_read(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_LP_EEE_ADV, &lp);  in elink_eee_an_resolve()
3992 static void elink_cl45_read_or_write(struct bxe_softc *sc, struct elink_phy *phy,  in elink_cl45_read_or_write()  argument
3996 	elink_cl45_read(sc, phy, devad, reg, &val);  in elink_cl45_read_or_write()
3997 	elink_cl45_write(sc, phy, devad, reg, val | or_val);  in elink_cl45_read_or_write()
4001 				      struct elink_phy *phy,  in elink_cl45_read_and_write()  argument
4005 	elink_cl45_read(sc, phy, devad, reg, &val);  in elink_cl45_read_and_write()
4006 	elink_cl45_write(sc, phy, devad, reg, val & and_val);  in elink_cl45_read_and_write()
4017 		if (params->phy[phy_index].addr == phy_addr) {  in elink_phy_read()
4019 					       &params->phy[phy_index], devad,  in elink_phy_read()
4034 		if (params->phy[phy_index].addr == phy_addr) {  in elink_phy_write()
4036 						&params->phy[phy_index], devad,  in elink_phy_write()
4043 static uint8_t elink_get_warpcore_lane(struct elink_phy *phy,  in elink_get_warpcore_lane()  argument
4099 			      struct elink_phy *phy)  in elink_set_aer_mmd()  argument
4108 	offset = (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) ?  in elink_set_aer_mmd()
4109 		(phy->addr + ser_lane) : 0;  in elink_set_aer_mmd()
4112 		aer_val = elink_get_warpcore_lane(phy, params);  in elink_set_aer_mmd()
4119 		if (phy->flags & ELINK_FLAGS_WC_DUAL_MODE)  in elink_set_aer_mmd()
4126 	CL22_WR_OVER_CL45(sc, phy, MDIO_REG_BANK_AER_BLOCK,  in elink_set_aer_mmd()
4168 static void elink_xgxs_specific_func(struct elink_phy *phy,  in elink_xgxs_specific_func()  argument
4178 		       phy->def_md_devad);  in elink_xgxs_specific_func()
4197 	elink_xgxs_specific_func(&params->phy[ELINK_INT_PHY], params,  in elink_xgxs_deassert()
4201 static void elink_calc_ieee_aneg_adv(struct elink_phy *phy,  in elink_calc_ieee_aneg_adv()  argument
4210 	switch (phy->req_flow_ctrl) {  in elink_calc_ieee_aneg_adv()
4259 		params->phy[actual_phy_idx].req_flow_ctrl =  in set_phy_vars()
4262 		params->phy[actual_phy_idx].req_line_speed =  in set_phy_vars()
4265 		params->phy[actual_phy_idx].speed_cap_mask =  in set_phy_vars()
4268 		params->phy[actual_phy_idx].req_duplex =  in set_phy_vars()
4277 			   params->phy[actual_phy_idx].req_flow_ctrl,  in set_phy_vars()
4278 			   params->phy[actual_phy_idx].req_line_speed,  in set_phy_vars()
4279 			   params->phy[actual_phy_idx].speed_cap_mask);  in set_phy_vars()
4284 				    struct elink_phy *phy,  in elink_ext_phy_set_pause()  argument
4290 	elink_cl45_read(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV_PAUSE, &val);  in elink_ext_phy_set_pause()
4295 	elink_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc);  in elink_ext_phy_set_pause()
4307 	elink_cl45_write(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV_PAUSE, val);  in elink_ext_phy_set_pause()
4310 static void elink_pause_resolve(struct elink_phy *phy,  in elink_pause_resolve()  argument
4357 static void elink_ext_phy_update_adv_fc(struct elink_phy *phy,  in elink_ext_phy_update_adv_fc()  argument
4365 	if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE) {  in elink_ext_phy_update_adv_fc()
4366 		elink_cl22_read(sc, phy, 0x4, &ld_pause);  in elink_ext_phy_update_adv_fc()
4367 		elink_cl22_read(sc, phy, 0x5, &lp_pause);  in elink_ext_phy_update_adv_fc()
4370 		uint8_t lane = elink_get_warpcore_lane(phy, params);  in elink_ext_phy_update_adv_fc()
4372 		elink_cl45_read(sc, phy,  in elink_ext_phy_update_adv_fc()
4379 			elink_cl45_read(sc, phy, MDIO_AN_DEVAD,  in elink_ext_phy_update_adv_fc()
4381 			elink_cl45_read(sc, phy, MDIO_AN_DEVAD,  in elink_ext_phy_update_adv_fc()
4384 			elink_cl45_read(sc, phy, MDIO_AN_DEVAD,  in elink_ext_phy_update_adv_fc()
4386 			elink_cl45_read(sc, phy, MDIO_AN_DEVAD,  in elink_ext_phy_update_adv_fc()
4396 		elink_cl45_read(sc, phy,  in elink_ext_phy_update_adv_fc()
4399 		elink_cl45_read(sc, phy,  in elink_ext_phy_update_adv_fc()
4408 	elink_pause_resolve(phy, params, vars, pause_result);  in elink_ext_phy_update_adv_fc()
4412 static uint8_t elink_ext_phy_resolve_fc(struct elink_phy *phy,  in elink_ext_phy_resolve_fc()  argument
4418 	if (phy->req_flow_ctrl != ELINK_FLOW_CTRL_AUTO) {  in elink_ext_phy_resolve_fc()
4420 		if (phy->req_line_speed == ELINK_SPEED_AUTO_NEG)  in elink_ext_phy_resolve_fc()
4421 			elink_ext_phy_update_adv_fc(phy, params, vars);  in elink_ext_phy_resolve_fc()
4423 		vars->flow_ctrl = phy->req_flow_ctrl;  in elink_ext_phy_resolve_fc()
4424 	} else if (phy->req_line_speed != ELINK_SPEED_AUTO_NEG)  in elink_ext_phy_resolve_fc()
4428 		elink_ext_phy_update_adv_fc(phy, params, vars);  in elink_ext_phy_resolve_fc()
4461 static void elink_warpcore_enable_AN_KR2(struct elink_phy *phy,  in elink_warpcore_enable_AN_KR2()  argument
4488 	elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD,  in elink_warpcore_enable_AN_KR2()
4492 		elink_cl45_write(sc, phy, reg_set[i].devad, reg_set[i].reg,  in elink_warpcore_enable_AN_KR2()
4502 			      struct elink_phy *phy)  in elink_disable_kr2()  argument
4527 		elink_cl45_write(sc, phy, reg_set[i].devad, reg_set[i].reg,  in elink_disable_kr2()
4535 static void elink_warpcore_set_lpi_passthrough(struct elink_phy *phy,  in elink_warpcore_set_lpi_passthrough()  argument
4541 	elink_cl45_write(sc, phy, MDIO_WC_DEVAD,  in elink_warpcore_set_lpi_passthrough()
4543 	elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD,  in elink_warpcore_set_lpi_passthrough()
4547 static void elink_warpcore_restart_AN_KR(struct elink_phy *phy,  in elink_warpcore_restart_AN_KR()  argument
4552 	uint16_t lane = elink_get_warpcore_lane(phy, params);  in elink_warpcore_restart_AN_KR()
4553 	CL22_WR_OVER_CL45(sc, phy, MDIO_REG_BANK_AER_BLOCK,  in elink_warpcore_restart_AN_KR()
4555 	elink_cl45_write(sc, phy, MDIO_AN_DEVAD,  in elink_warpcore_restart_AN_KR()
4559 	elink_set_aer_mmd(params, phy);  in elink_warpcore_restart_AN_KR()
4562 static void elink_warpcore_enable_AN_KR(struct elink_phy *phy,  in elink_warpcore_enable_AN_KR()  argument
4581 		elink_cl45_write(sc, phy, reg_set[i].devad, reg_set[i].reg,  in elink_warpcore_enable_AN_KR()
4584 	elink_cl45_read(sc, phy, MDIO_WC_DEVAD,  in elink_warpcore_enable_AN_KR()
4588 	elink_cl45_write(sc, phy, MDIO_WC_DEVAD,  in elink_warpcore_enable_AN_KR()
4593 	     (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) ||  in elink_warpcore_enable_AN_KR()
4599 		elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD, addr, 0x1);  in elink_warpcore_enable_AN_KR()
4603 	     (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) ||  in elink_warpcore_enable_AN_KR()
4608 		CL22_WR_OVER_CL45(sc, phy, MDIO_REG_BANK_AER_BLOCK,  in elink_warpcore_enable_AN_KR()
4611 		elink_cl45_write(sc, phy, MDIO_AN_DEVAD,  in elink_warpcore_enable_AN_KR()
4613 		elink_set_aer_mmd(params, phy);  in elink_warpcore_enable_AN_KR()
4618 	lane = elink_get_warpcore_lane(phy, params);  in elink_warpcore_enable_AN_KR()
4619 	elink_cl45_write(sc, phy, MDIO_WC_DEVAD,  in elink_warpcore_enable_AN_KR()
4623 	if (phy->flags & ELINK_FLAGS_WC_DUAL_MODE)  in elink_warpcore_enable_AN_KR()
4624 		elink_cl45_write(sc, phy, MDIO_WC_DEVAD,  in elink_warpcore_enable_AN_KR()
4627 	elink_cl45_write(sc, phy, MDIO_WC_DEVAD,  in elink_warpcore_enable_AN_KR()
4630 	elink_cl45_write(sc, phy, MDIO_WC_DEVAD,  in elink_warpcore_enable_AN_KR()
4635 	elink_cl45_write(sc, phy, MDIO_AN_DEVAD,  in elink_warpcore_enable_AN_KR()
4639 	elink_cl45_write(sc, phy, MDIO_AN_DEVAD,  in elink_warpcore_enable_AN_KR()
4649 		elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD,  in elink_warpcore_enable_AN_KR()
4656 	elink_ext_phy_set_pause(params, phy, vars);  in elink_warpcore_enable_AN_KR()
4658 	elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD,  in elink_warpcore_enable_AN_KR()
4662 	elink_cl45_write(sc, phy, MDIO_WC_DEVAD,  in elink_warpcore_enable_AN_KR()
4665 	if (((phy->req_line_speed == ELINK_SPEED_AUTO_NEG) &&  in elink_warpcore_enable_AN_KR()
4666 	     (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_20G)) ||  in elink_warpcore_enable_AN_KR()
4667 	    (phy->req_line_speed == ELINK_SPEED_20000)) {  in elink_warpcore_enable_AN_KR()
4669 		CL22_WR_OVER_CL45(sc, phy, MDIO_REG_BANK_AER_BLOCK,  in elink_warpcore_enable_AN_KR()
4672 		elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD,  in elink_warpcore_enable_AN_KR()
4676 		elink_cl45_write(sc, phy, MDIO_WC_DEVAD,  in elink_warpcore_enable_AN_KR()
4678 		elink_set_aer_mmd(params, phy);  in elink_warpcore_enable_AN_KR()
4680 		elink_warpcore_enable_AN_KR2(phy, params, vars);  in elink_warpcore_enable_AN_KR()
4683 		elink_cl45_write(sc, phy, MDIO_WC_DEVAD,  in elink_warpcore_enable_AN_KR()
4688 		elink_cl45_read(sc, phy, MDIO_WC_DEVAD,  in elink_warpcore_enable_AN_KR()
4703 		elink_cl45_write(sc, phy, MDIO_WC_DEVAD,  in elink_warpcore_enable_AN_KR()
4707 		elink_disable_kr2(params, vars, phy);  in elink_warpcore_enable_AN_KR()
4711 	elink_warpcore_restart_AN_KR(phy, params);  in elink_warpcore_enable_AN_KR()
4714 static void elink_warpcore_set_10G_KR(struct elink_phy *phy,  in elink_warpcore_set_10G_KR()  argument
4734 		elink_cl45_write(sc, phy, reg_set[i].devad, reg_set[i].reg,  in elink_warpcore_set_10G_KR()
4737 	lane = elink_get_warpcore_lane(phy, params);  in elink_warpcore_set_10G_KR()
4739 	CL22_WR_OVER_CL45(sc, phy, MDIO_REG_BANK_AER_BLOCK,  in elink_warpcore_set_10G_KR()
4742 	elink_cl45_read(sc, phy, MDIO_WC_DEVAD,  in elink_warpcore_set_10G_KR()
4745 	elink_cl45_write(sc, phy, MDIO_WC_DEVAD,  in elink_warpcore_set_10G_KR()
4748 	elink_cl45_read(sc, phy, MDIO_WC_DEVAD,  in elink_warpcore_set_10G_KR()
4751 	elink_cl45_write(sc, phy, MDIO_WC_DEVAD,  in elink_warpcore_set_10G_KR()
4754 	elink_set_aer_mmd(params, phy);  in elink_warpcore_set_10G_KR()
4756 	elink_cl45_write(sc, phy, MDIO_PMA_DEVAD,  in elink_warpcore_set_10G_KR()
4759 	elink_cl45_write(sc, phy, MDIO_PMA_DEVAD,  in elink_warpcore_set_10G_KR()
4763 	elink_cl45_write(sc, phy, MDIO_WC_DEVAD,  in elink_warpcore_set_10G_KR()
4767 	elink_cl45_write(sc, phy, MDIO_WC_DEVAD,  in elink_warpcore_set_10G_KR()
4771 	elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD,  in elink_warpcore_set_10G_KR()
4775 	elink_cl45_write(sc, phy, MDIO_WC_DEVAD,  in elink_warpcore_set_10G_KR()
4777 	elink_cl45_write(sc, phy, MDIO_WC_DEVAD,  in elink_warpcore_set_10G_KR()
4782 static void elink_warpcore_set_10G_XFI(struct elink_phy *phy,  in elink_warpcore_set_10G_XFI()  argument
4791 	elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD,  in elink_warpcore_set_10G_XFI()
4795 	elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD,  in elink_warpcore_set_10G_XFI()
4799 	elink_cl45_write(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0);  in elink_warpcore_set_10G_XFI()
4802 	elink_cl45_read_and_write(sc, phy, MDIO_WC_DEVAD,  in elink_warpcore_set_10G_XFI()
4806 	elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD,  in elink_warpcore_set_10G_XFI()
4810 	elink_cl45_read_and_write(sc, phy, MDIO_WC_DEVAD,  in elink_warpcore_set_10G_XFI()
4814 	elink_cl45_read_and_write(sc, phy, MDIO_WC_DEVAD,  in elink_warpcore_set_10G_XFI()
4819 	elink_cl45_read(sc, phy, MDIO_WC_DEVAD,  in elink_warpcore_set_10G_XFI()
4821 	elink_cl45_write(sc, phy, MDIO_WC_DEVAD,  in elink_warpcore_set_10G_XFI()
4826 	elink_cl45_read(sc, phy, MDIO_WC_DEVAD,  in elink_warpcore_set_10G_XFI()
4882 	elink_cl45_write(sc, phy, MDIO_WC_DEVAD,  in elink_warpcore_set_10G_XFI()
4886 	lane = elink_get_warpcore_lane(phy, params);  in elink_warpcore_set_10G_XFI()
4887 	elink_cl45_write(sc, phy, MDIO_WC_DEVAD,  in elink_warpcore_set_10G_XFI()
4890 	elink_cl45_write(sc, phy, MDIO_WC_DEVAD,  in elink_warpcore_set_10G_XFI()
4895 	elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD,  in elink_warpcore_set_10G_XFI()
4899 	elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD,  in elink_warpcore_set_10G_XFI()
4902 	elink_warpcore_set_lpi_passthrough(phy, params);  in elink_warpcore_set_10G_XFI()
4905 	elink_cl45_write(sc, phy, MDIO_WC_DEVAD,  in elink_warpcore_set_10G_XFI()
4909 	elink_cl45_read_and_write(sc, phy, MDIO_WC_DEVAD,  in elink_warpcore_set_10G_XFI()
4913 	elink_cl45_read_and_write(sc, phy, MDIO_WC_DEVAD,  in elink_warpcore_set_10G_XFI()
4917 static void elink_warpcore_set_20G_force_KR2(struct elink_phy *phy,  in elink_warpcore_set_20G_force_KR2()  argument
4923 	CL22_WR_OVER_CL45(sc, phy, MDIO_REG_BANK_AER_BLOCK,  in elink_warpcore_set_20G_force_KR2()
4927 	elink_cl45_read_and_write(sc, phy, MDIO_WC_DEVAD,  in elink_warpcore_set_20G_force_KR2()
4930 	elink_set_aer_mmd(params, phy);  in elink_warpcore_set_20G_force_KR2()
4932 	elink_cl45_read_and_write(sc, phy, MDIO_PMA_DEVAD,  in elink_warpcore_set_20G_force_KR2()
4934 	elink_cl45_write(sc, phy, MDIO_AN_DEVAD,  in elink_warpcore_set_20G_force_KR2()
4937 	elink_cl45_read(sc, phy, MDIO_WC_DEVAD,  in elink_warpcore_set_20G_force_KR2()
4941 	elink_cl45_write(sc, phy, MDIO_WC_DEVAD,  in elink_warpcore_set_20G_force_KR2()
4945 	elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD,  in elink_warpcore_set_20G_force_KR2()
4948 	elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD,  in elink_warpcore_set_20G_force_KR2()
4951 	elink_cl45_read(sc, phy, MDIO_WC_DEVAD,  in elink_warpcore_set_20G_force_KR2()
4955 	elink_cl45_write(sc, phy, MDIO_WC_DEVAD,  in elink_warpcore_set_20G_force_KR2()
4957 	elink_cl45_write(sc, phy, MDIO_WC_DEVAD,  in elink_warpcore_set_20G_force_KR2()
4961 	CL22_WR_OVER_CL45(sc, phy, MDIO_REG_BANK_AER_BLOCK,  in elink_warpcore_set_20G_force_KR2()
4964 	elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD,  in elink_warpcore_set_20G_force_KR2()
4967 	elink_set_aer_mmd(params, phy);  in elink_warpcore_set_20G_force_KR2()
4971 					 struct elink_phy *phy,  in elink_warpcore_set_20G_DXGXS()  argument
4975 	elink_cl45_write(sc, phy, MDIO_WC_DEVAD,  in elink_warpcore_set_20G_DXGXS()
4979 	elink_cl45_write(sc, phy, MDIO_WC_DEVAD,  in elink_warpcore_set_20G_DXGXS()
4982 	elink_cl45_write(sc, phy, MDIO_WC_DEVAD,  in elink_warpcore_set_20G_DXGXS()
4985 	elink_cl45_write(sc, phy, MDIO_WC_DEVAD,  in elink_warpcore_set_20G_DXGXS()
4988 	elink_cl45_write(sc, phy, MDIO_WC_DEVAD,  in elink_warpcore_set_20G_DXGXS()
4991 	elink_cl45_write(sc, phy, MDIO_WC_DEVAD,  in elink_warpcore_set_20G_DXGXS()
4994 	elink_cl45_write(sc, phy, MDIO_WC_DEVAD,  in elink_warpcore_set_20G_DXGXS()
4997 	elink_cl45_write(sc, phy, MDIO_WC_DEVAD,  in elink_warpcore_set_20G_DXGXS()
5000 	elink_cl45_write(sc, phy, MDIO_WC_DEVAD,  in elink_warpcore_set_20G_DXGXS()
5003 	elink_cl45_write(sc, phy, MDIO_WC_DEVAD,  in elink_warpcore_set_20G_DXGXS()
5007 	elink_cl45_write(sc, phy, MDIO_WC_DEVAD,  in elink_warpcore_set_20G_DXGXS()
5011 	elink_cl45_write(sc, phy, MDIO_WC_DEVAD,  in elink_warpcore_set_20G_DXGXS()
5015 	elink_cl45_write(sc, phy, MDIO_WC_DEVAD,  in elink_warpcore_set_20G_DXGXS()
5019 	elink_cl45_write(sc, phy, MDIO_WC_DEVAD,  in elink_warpcore_set_20G_DXGXS()
5024 static void elink_warpcore_set_sgmii_speed(struct elink_phy *phy,  in elink_warpcore_set_sgmii_speed()  argument
5033 	elink_cl45_read_and_write(sc, phy, MDIO_WC_DEVAD,  in elink_warpcore_set_sgmii_speed()
5036 	elink_warpcore_set_lpi_passthrough(phy, params);  in elink_warpcore_set_sgmii_speed()
5038 	if (always_autoneg || phy->req_line_speed == ELINK_SPEED_AUTO_NEG) {  in elink_warpcore_set_sgmii_speed()
5040 		elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD,  in elink_warpcore_set_sgmii_speed()
5045 		elink_cl45_read(sc, phy, MDIO_WC_DEVAD,  in elink_warpcore_set_sgmii_speed()
5048 		switch (phy->req_line_speed) {  in elink_warpcore_set_sgmii_speed()
5059 			   "Speed not supported: 0x%x\n", phy->req_line_speed);  in elink_warpcore_set_sgmii_speed()
5063 		if (phy->req_duplex == DUPLEX_FULL)  in elink_warpcore_set_sgmii_speed()
5066 		elink_cl45_write(sc, phy, MDIO_WC_DEVAD,  in elink_warpcore_set_sgmii_speed()
5070 			       phy->req_line_speed);  in elink_warpcore_set_sgmii_speed()
5071 		elink_cl45_read(sc, phy, MDIO_WC_DEVAD,  in elink_warpcore_set_sgmii_speed()
5077 	elink_cl45_read(sc, phy, MDIO_WC_DEVAD,  in elink_warpcore_set_sgmii_speed()
5084 	elink_cl45_write(sc, phy, MDIO_WC_DEVAD,  in elink_warpcore_set_sgmii_speed()
5089 	elink_cl45_read(sc, phy, MDIO_WC_DEVAD,  in elink_warpcore_set_sgmii_speed()
5091 	elink_cl45_write(sc, phy, MDIO_WC_DEVAD,  in elink_warpcore_set_sgmii_speed()
5096 	elink_cl45_write(sc, phy, MDIO_WC_DEVAD,  in elink_warpcore_set_sgmii_speed()
5101 	elink_cl45_write(sc, phy, MDIO_WC_DEVAD,  in elink_warpcore_set_sgmii_speed()
5108 				      struct elink_phy *phy,  in elink_warpcore_reset_lane()  argument
5113 	elink_cl45_read(sc, phy, MDIO_WC_DEVAD,  in elink_warpcore_reset_lane()
5119 	elink_cl45_write(sc, phy, MDIO_WC_DEVAD,  in elink_warpcore_reset_lane()
5121 	elink_cl45_read(sc, phy, MDIO_WC_DEVAD,  in elink_warpcore_reset_lane()
5126 static void elink_warpcore_clear_regs(struct elink_phy *phy,  in elink_warpcore_clear_regs()  argument
5149 	elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD,  in elink_warpcore_clear_regs()
5153 		elink_cl45_write(sc, phy, wc_regs[i].devad, wc_regs[i].reg,  in elink_warpcore_clear_regs()
5156 	lane = elink_get_warpcore_lane(phy, params);  in elink_warpcore_clear_regs()
5157 	elink_cl45_write(sc, phy, MDIO_WC_DEVAD,  in elink_warpcore_clear_regs()
5201 static int elink_is_sfp_module_plugged(struct elink_phy *phy,  in elink_is_sfp_module_plugged()  argument
5219 static int elink_warpcore_get_sigdet(struct elink_phy *phy,  in elink_warpcore_get_sigdet()  argument
5225 	lane = elink_get_warpcore_lane(phy, params);  in elink_warpcore_get_sigdet()
5227 	elink_cl45_read(sc, phy, MDIO_WC_DEVAD, MDIO_WC_REG_GP2_STATUS_GP_2_0,  in elink_warpcore_get_sigdet()
5233 static void elink_warpcore_config_runtime(struct elink_phy *phy,  in elink_warpcore_config_runtime()  argument
5247 		uint16_t lane = elink_get_warpcore_lane(phy, params);  in elink_warpcore_config_runtime()
5256 			elink_cl45_read(sc, phy, MDIO_WC_DEVAD, 0x81d1,  in elink_warpcore_config_runtime()
5266 				elink_warpcore_reset_lane(sc, phy, 1);  in elink_warpcore_config_runtime()
5267 				elink_warpcore_reset_lane(sc, phy, 0);  in elink_warpcore_config_runtime()
5270 				elink_cl45_write(sc, phy, MDIO_AN_DEVAD,  in elink_warpcore_config_runtime()
5286 static void elink_warpcore_config_sfi(struct elink_phy *phy,  in elink_warpcore_config_sfi()  argument
5289 	uint16_t lane = elink_get_warpcore_lane(phy, params);  in elink_warpcore_config_sfi()
5291 	elink_warpcore_clear_regs(phy, params, lane);  in elink_warpcore_config_sfi()
5294 	    (phy->media_type != ELINK_ETH_PHY_SFP_1G_FIBER)) {  in elink_warpcore_config_sfi()
5296 		elink_warpcore_set_10G_XFI(phy, params, 0);  in elink_warpcore_config_sfi()
5299 		elink_warpcore_set_sgmii_speed(phy, params, 1, 0);  in elink_warpcore_config_sfi()
5304 					 struct elink_phy *phy,  in elink_sfp_e3_set_transmitter()  argument
5320 	if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_20G)  in elink_sfp_e3_set_transmitter()
5324 static void elink_warpcore_config_init(struct elink_phy *phy,  in elink_warpcore_config_init()  argument
5331 	uint16_t lane = elink_get_warpcore_lane(phy, params);  in elink_warpcore_config_init()
5339 	elink_set_aer_mmd(params, phy);  in elink_warpcore_config_init()
5340 	elink_warpcore_reset_lane(sc, phy, 1);  in elink_warpcore_config_init()
5343 	    (phy->req_line_speed &&  in elink_warpcore_config_init()
5344 	     ((phy->req_line_speed == ELINK_SPEED_100) ||  in elink_warpcore_config_init()
5345 	      (phy->req_line_speed == ELINK_SPEED_10)))) {  in elink_warpcore_config_init()
5348 		elink_warpcore_clear_regs(phy, params, lane);  in elink_warpcore_config_init()
5349 		elink_warpcore_set_sgmii_speed(phy, params, 0, 1);  in elink_warpcore_config_init()
5355 				elink_warpcore_enable_AN_KR(phy, params, vars);  in elink_warpcore_config_init()
5358 				elink_warpcore_set_10G_KR(phy, params, vars);  in elink_warpcore_config_init()
5363 			elink_warpcore_clear_regs(phy, params, lane);  in elink_warpcore_config_init()
5366 				elink_warpcore_set_10G_XFI(phy, params, 1);  in elink_warpcore_config_init()
5375 				elink_warpcore_set_sgmii_speed(phy,  in elink_warpcore_config_init()
5390 				if (elink_is_sfp_module_plugged(phy, params))  in elink_warpcore_config_init()
5391 					elink_sfp_module_detection(phy, params);  in elink_warpcore_config_init()
5394 								     phy, 1);  in elink_warpcore_config_init()
5397 			elink_warpcore_config_sfi(phy, params);  in elink_warpcore_config_init()
5406 			elink_warpcore_set_20G_DXGXS(sc, phy, lane);  in elink_warpcore_config_init()
5409 			elink_sfp_module_detection(phy, params);  in elink_warpcore_config_init()
5413 				elink_warpcore_enable_AN_KR(phy, params, vars);  in elink_warpcore_config_init()
5416 				elink_warpcore_set_20G_force_KR2(phy, params);  in elink_warpcore_config_init()
5428 	elink_warpcore_reset_lane(sc, phy, 0);  in elink_warpcore_config_init()
5432 static void elink_warpcore_link_reset(struct elink_phy *phy,  in elink_warpcore_link_reset()  argument
5437 	elink_sfp_e3_set_transmitter(params, phy, 0);  in elink_warpcore_link_reset()
5439 	elink_set_aer_mmd(params, phy);  in elink_warpcore_link_reset()
5441 	elink_warpcore_reset_lane(sc, phy, 1);  in elink_warpcore_link_reset()
5445 	elink_cl45_read_and_write(sc, phy, MDIO_WC_DEVAD,  in elink_warpcore_link_reset()
5448 	elink_cl45_read_and_write(sc, phy, MDIO_WC_DEVAD,  in elink_warpcore_link_reset()
5452 	CL22_WR_OVER_CL45(sc, phy, MDIO_REG_BANK_AER_BLOCK,  in elink_warpcore_link_reset()
5455 	elink_cl45_read_and_write(sc, phy, MDIO_WC_DEVAD,  in elink_warpcore_link_reset()
5459 	elink_cl45_read_and_write(sc, phy, MDIO_WC_DEVAD,  in elink_warpcore_link_reset()
5461 	lane = elink_get_warpcore_lane(phy, params);  in elink_warpcore_link_reset()
5463 	elink_cl45_read(sc, phy, MDIO_WC_DEVAD,  in elink_warpcore_link_reset()
5466 	if (phy->flags & ELINK_FLAGS_WC_DUAL_MODE)  in elink_warpcore_link_reset()
5468 	elink_cl45_write(sc, phy, MDIO_WC_DEVAD,  in elink_warpcore_link_reset()
5471 	elink_cl45_read(sc, phy, MDIO_WC_DEVAD,  in elink_warpcore_link_reset()
5475 	if (phy->flags & ELINK_FLAGS_WC_DUAL_MODE) {  in elink_warpcore_link_reset()
5480 	elink_cl45_write(sc, phy, MDIO_WC_DEVAD,  in elink_warpcore_link_reset()
5483 	elink_set_aer_mmd(params, phy);  in elink_warpcore_link_reset()
5487 static void elink_set_warpcore_loopback(struct elink_phy *phy,  in elink_set_warpcore_loopback()  argument
5494 		       params->loopback_mode, phy->req_line_speed);  in elink_set_warpcore_loopback()
5496 	if (phy->req_line_speed < ELINK_SPEED_10000 ||  in elink_set_warpcore_loopback()
5497 	    phy->supported & ELINK_SUPPORTED_20000baseKR2_Full) {  in elink_set_warpcore_loopback()
5501 		CL22_WR_OVER_CL45(sc, phy, MDIO_REG_BANK_AER_BLOCK,  in elink_set_warpcore_loopback()
5504 		elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD,  in elink_set_warpcore_loopback()
5508 		lane = elink_get_warpcore_lane(phy, params);  in elink_set_warpcore_loopback()
5509 		elink_cl45_read(sc, phy, MDIO_WC_DEVAD,  in elink_set_warpcore_loopback()
5512 		if (phy->flags & ELINK_FLAGS_WC_DUAL_MODE)  in elink_set_warpcore_loopback()
5514 		elink_cl45_write(sc, phy, MDIO_WC_DEVAD,  in elink_set_warpcore_loopback()
5519 		elink_set_aer_mmd(params, phy);  in elink_set_warpcore_loopback()
5522 		elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD,  in elink_set_warpcore_loopback()
5525 		elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD,  in elink_set_warpcore_loopback()
5670 	params->phy[ELINK_INT_PHY].media_type =  in elink_link_status_update()
5673 	params->phy[ELINK_EXT_PHY1].media_type =  in elink_link_status_update()
5676 	params->phy[ELINK_EXT_PHY2].media_type =  in elink_link_status_update()
5707 				struct elink_phy *phy)  in elink_set_master_ln()  argument
5716 	CL22_RD_OVER_CL45(sc, phy,  in elink_set_master_ln()
5721 	CL22_WR_OVER_CL45(sc, phy,  in elink_set_master_ln()
5728 			       struct elink_phy *phy,  in elink_reset_unicore()  argument
5734 	CL22_RD_OVER_CL45(sc, phy,  in elink_reset_unicore()
5739 	CL22_WR_OVER_CL45(sc, phy,  in elink_reset_unicore()
5752 		CL22_RD_OVER_CL45(sc, phy,  in elink_reset_unicore()
5772 				 struct elink_phy *phy)  in elink_set_swap_lanes()  argument
5788 		CL22_WR_OVER_CL45(sc, phy,  in elink_set_swap_lanes()
5795 		CL22_WR_OVER_CL45(sc, phy,  in elink_set_swap_lanes()
5801 		CL22_WR_OVER_CL45(sc, phy,  in elink_set_swap_lanes()
5807 		CL22_WR_OVER_CL45(sc, phy,  in elink_set_swap_lanes()
5813 static void elink_set_parallel_detection(struct elink_phy *phy,  in elink_set_parallel_detection()  argument
5818 	CL22_RD_OVER_CL45(sc, phy,  in elink_set_parallel_detection()
5822 	if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)  in elink_set_parallel_detection()
5827 		phy->speed_cap_mask, control2);  in elink_set_parallel_detection()
5828 	CL22_WR_OVER_CL45(sc, phy,  in elink_set_parallel_detection()
5833 	if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) &&  in elink_set_parallel_detection()
5834 	     (phy->speed_cap_mask &  in elink_set_parallel_detection()
5838 		CL22_WR_OVER_CL45(sc, phy,  in elink_set_parallel_detection()
5843 		CL22_RD_OVER_CL45(sc, phy,  in elink_set_parallel_detection()
5852 		CL22_WR_OVER_CL45(sc, phy,  in elink_set_parallel_detection()
5858 		CL22_WR_OVER_CL45(sc, phy,  in elink_set_parallel_detection()
5866 static void elink_set_autoneg(struct elink_phy *phy,  in elink_set_autoneg()  argument
5875 	CL22_RD_OVER_CL45(sc, phy,  in elink_set_autoneg()
5886 	CL22_WR_OVER_CL45(sc, phy,  in elink_set_autoneg()
5892 	CL22_RD_OVER_CL45(sc, phy,  in elink_set_autoneg()
5903 	CL22_WR_OVER_CL45(sc, phy,  in elink_set_autoneg()
5908 	CL22_RD_OVER_CL45(sc, phy,  in elink_set_autoneg()
5921 	CL22_WR_OVER_CL45(sc, phy,  in elink_set_autoneg()
5928 		CL22_WR_OVER_CL45(sc, phy,  in elink_set_autoneg()
5934 		CL22_WR_OVER_CL45(sc, phy,  in elink_set_autoneg()
5942 		CL22_RD_OVER_CL45(sc, phy,  in elink_set_autoneg()
5946 		if (phy->speed_cap_mask &  in elink_set_autoneg()
5949 		if (phy->speed_cap_mask &  in elink_set_autoneg()
5953 		CL22_WR_OVER_CL45(sc, phy,  in elink_set_autoneg()
5964 	CL22_WR_OVER_CL45(sc, phy,  in elink_set_autoneg()
5970 static void elink_program_serdes(struct elink_phy *phy,  in elink_program_serdes()  argument
5978 	CL22_RD_OVER_CL45(sc, phy,  in elink_program_serdes()
5984 	if (phy->req_duplex == DUPLEX_FULL)  in elink_program_serdes()
5986 	CL22_WR_OVER_CL45(sc, phy,  in elink_program_serdes()
5993 	CL22_RD_OVER_CL45(sc, phy,  in elink_program_serdes()
6013 	CL22_WR_OVER_CL45(sc, phy,  in elink_program_serdes()
6019 static void elink_set_brcm_cl37_advertisement(struct elink_phy *phy,  in elink_set_brcm_cl37_advertisement()  argument
6026 	if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G)  in elink_set_brcm_cl37_advertisement()
6028 	if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)  in elink_set_brcm_cl37_advertisement()
6030 	CL22_WR_OVER_CL45(sc, phy,  in elink_set_brcm_cl37_advertisement()
6034 	CL22_WR_OVER_CL45(sc, phy,  in elink_set_brcm_cl37_advertisement()
6039 static void elink_set_ieee_aneg_advertisement(struct elink_phy *phy,  in elink_set_ieee_aneg_advertisement()  argument
6047 	CL22_WR_OVER_CL45(sc, phy,  in elink_set_ieee_aneg_advertisement()
6050 	CL22_RD_OVER_CL45(sc, phy,  in elink_set_ieee_aneg_advertisement()
6055 	CL22_WR_OVER_CL45(sc, phy,  in elink_set_ieee_aneg_advertisement()
6060 static void elink_restart_autoneg(struct elink_phy *phy,  in elink_restart_autoneg()  argument
6071 		CL22_RD_OVER_CL45(sc, phy,  in elink_restart_autoneg()
6076 		CL22_WR_OVER_CL45(sc, phy,  in elink_restart_autoneg()
6084 		CL22_RD_OVER_CL45(sc, phy,  in elink_restart_autoneg()
6091 		CL22_WR_OVER_CL45(sc, phy,  in elink_restart_autoneg()
6100 static void elink_initialize_sgmii_process(struct elink_phy *phy,  in elink_initialize_sgmii_process()  argument
6109 	CL22_RD_OVER_CL45(sc, phy,  in elink_initialize_sgmii_process()
6118 	CL22_WR_OVER_CL45(sc, phy,  in elink_initialize_sgmii_process()
6128 		CL22_RD_OVER_CL45(sc, phy,  in elink_initialize_sgmii_process()
6156 		if (phy->req_duplex == DUPLEX_FULL)  in elink_initialize_sgmii_process()
6159 		CL22_WR_OVER_CL45(sc, phy,  in elink_initialize_sgmii_process()
6166 		elink_restart_autoneg(phy, params, 0);  in elink_initialize_sgmii_process()
6172 static elink_status_t elink_direct_parallel_detect_used(struct elink_phy *phy,  in elink_direct_parallel_detect_used()  argument
6177 	if (phy->req_line_speed != ELINK_SPEED_AUTO_NEG)  in elink_direct_parallel_detect_used()
6179 	CL22_RD_OVER_CL45(sc, phy,  in elink_direct_parallel_detect_used()
6183 	CL22_RD_OVER_CL45(sc, phy,  in elink_direct_parallel_detect_used()
6193 	CL22_RD_OVER_CL45(sc, phy,  in elink_direct_parallel_detect_used()
6206 static void elink_update_adv_fc(struct elink_phy *phy,  in elink_update_adv_fc()  argument
6221 		CL22_RD_OVER_CL45(sc, phy,  in elink_update_adv_fc()
6225 		CL22_RD_OVER_CL45(sc, phy,  in elink_update_adv_fc()
6235 		CL22_RD_OVER_CL45(sc, phy,  in elink_update_adv_fc()
6239 		CL22_RD_OVER_CL45(sc, phy,  in elink_update_adv_fc()
6249 	elink_pause_resolve(phy, params, vars, pause_result);  in elink_update_adv_fc()
6253 static void elink_flow_ctrl_resolve(struct elink_phy *phy,  in elink_flow_ctrl_resolve()  argument
6262 	if (phy->req_flow_ctrl != ELINK_FLOW_CTRL_AUTO) {  in elink_flow_ctrl_resolve()
6264 		if (phy->req_line_speed == ELINK_SPEED_AUTO_NEG)  in elink_flow_ctrl_resolve()
6265 			elink_update_adv_fc(phy, params, vars, gp_status);  in elink_flow_ctrl_resolve()
6267 		vars->flow_ctrl = phy->req_flow_ctrl;  in elink_flow_ctrl_resolve()
6268 	} else if (phy->req_line_speed != ELINK_SPEED_AUTO_NEG)  in elink_flow_ctrl_resolve()
6272 		if (elink_direct_parallel_detect_used(phy, params)) {  in elink_flow_ctrl_resolve()
6276 		elink_update_adv_fc(phy, params, vars, gp_status);  in elink_flow_ctrl_resolve()
6281 static void elink_check_fallback_to_cl37(struct elink_phy *phy,  in elink_check_fallback_to_cl37()  argument
6288 	CL22_RD_OVER_CL45(sc, phy,  in elink_check_fallback_to_cl37()
6296 		CL22_WR_OVER_CL45(sc, phy,  in elink_check_fallback_to_cl37()
6303 	CL22_RD_OVER_CL45(sc, phy,  in elink_check_fallback_to_cl37()
6319 	CL22_RD_OVER_CL45(sc, phy,  in elink_check_fallback_to_cl37()
6340 	CL22_WR_OVER_CL45(sc, phy,  in elink_check_fallback_to_cl37()
6345 	elink_restart_autoneg(phy, params, 0);  in elink_check_fallback_to_cl37()
6349 static void elink_xgxs_an_resolve(struct elink_phy *phy,  in elink_xgxs_an_resolve()  argument
6358 	if (elink_direct_parallel_detect_used(phy, params))  in elink_xgxs_an_resolve()
6362 static elink_status_t elink_get_link_speed_duplex(struct elink_phy *phy,  in elink_get_link_speed_duplex()  argument
6370 	if (phy->req_line_speed == ELINK_SPEED_AUTO_NEG)  in elink_get_link_speed_duplex()
6455 static elink_status_t elink_link_settings_status(struct elink_phy *phy,  in elink_link_settings_status()  argument
6465 	CL22_RD_OVER_CL45(sc, phy,  in elink_link_settings_status()
6484 	rc = elink_get_link_speed_duplex(phy, params, vars, link_up, speed_mask,  in elink_link_settings_status()
6492 			elink_flow_ctrl_resolve(phy, params, vars, gp_status);  in elink_link_settings_status()
6493 			if (phy->req_line_speed == ELINK_SPEED_AUTO_NEG)  in elink_link_settings_status()
6494 				elink_xgxs_an_resolve(phy, params, vars,  in elink_link_settings_status()
6498 		if ((phy->req_line_speed == ELINK_SPEED_AUTO_NEG) &&  in elink_link_settings_status()
6501 			elink_check_fallback_to_cl37(phy, params);  in elink_link_settings_status()
6510 		CL22_RD_OVER_CL45(sc, phy, MDIO_REG_BANK_CL73_IEEEB1,  in elink_link_settings_status()
6521 		CL22_RD_OVER_CL45(sc, phy, MDIO_REG_BANK_OVER_1G,  in elink_link_settings_status()
6537 static elink_status_t elink_warpcore_read_status(struct elink_phy *phy,  in elink_warpcore_read_status()  argument
6545 	lane = elink_get_warpcore_lane(phy, params);  in elink_warpcore_read_status()
6548 	    (phy->flags & ELINK_FLAGS_WC_DUAL_MODE)) {  in elink_warpcore_read_status()
6549 		elink_cl45_read(sc, phy, MDIO_WC_DEVAD,  in elink_warpcore_read_status()
6551 		elink_cl45_read(sc, phy, MDIO_WC_DEVAD,  in elink_warpcore_read_status()
6556 	} else if ((phy->req_line_speed > ELINK_SPEED_10000) &&  in elink_warpcore_read_status()
6557 		(phy->supported & ELINK_SUPPORTED_20000baseMLD2_Full)) {  in elink_warpcore_read_status()
6559 		elink_cl45_read(sc, phy, MDIO_WC_DEVAD,  in elink_warpcore_read_status()
6561 		elink_cl45_read(sc, phy, MDIO_WC_DEVAD,  in elink_warpcore_read_status()
6567 			elink_ext_phy_resolve_fc(phy, params, vars);  in elink_warpcore_read_status()
6569 		elink_cl45_read(sc, phy, MDIO_WC_DEVAD,  in elink_warpcore_read_status()
6578 		if (phy->supported & ELINK_SUPPORTED_20000baseKR2_Full) {  in elink_warpcore_read_status()
6580 			elink_cl45_read(sc, phy, MDIO_AN_DEVAD,  in elink_warpcore_read_status()
6582 			elink_cl45_read(sc, phy, MDIO_AN_DEVAD,  in elink_warpcore_read_status()
6590 			if (phy->req_line_speed == ELINK_SPEED_AUTO_NEG) {  in elink_warpcore_read_status()
6592 				elink_cl45_read(sc, phy, MDIO_WC_DEVAD,  in elink_warpcore_read_status()
6600 				elink_cl45_read(sc, phy, MDIO_WC_DEVAD,  in elink_warpcore_read_status()
6609 			elink_ext_phy_resolve_fc(phy, params, vars);  in elink_warpcore_read_status()
6621 		elink_cl45_read(sc, phy, MDIO_AN_DEVAD,  in elink_warpcore_read_status()
6633 		elink_cl45_read(sc, phy, MDIO_WC_DEVAD,  in elink_warpcore_read_status()
6649 		elink_cl45_read(sc, phy, MDIO_WC_DEVAD,  in elink_warpcore_read_status()
6652 		elink_cl45_read(sc, phy, MDIO_WC_DEVAD,  in elink_warpcore_read_status()
6663 	rc = elink_get_link_speed_duplex(phy, params, vars, link_up, gp_speed,  in elink_warpcore_read_status()
6667 	if ((!link_up) && (phy->media_type == ELINK_ETH_PHY_KR) &&  in elink_warpcore_read_status()
6668 	    (!(phy->flags & ELINK_FLAGS_WC_DUAL_MODE)))  in elink_warpcore_read_status()
6678 	struct elink_phy *phy = &params->phy[ELINK_INT_PHY];  in elink_set_gmii_tx_driver()  local
6684 	CL22_RD_OVER_CL45(sc, phy,  in elink_set_gmii_tx_driver()
6698 		CL22_RD_OVER_CL45(sc, phy,  in elink_set_gmii_tx_driver()
6707 			CL22_WR_OVER_CL45(sc, phy,  in elink_set_gmii_tx_driver()
6761 static void elink_set_preemphasis(struct elink_phy *phy,  in elink_set_preemphasis()  argument
6770 			CL22_WR_OVER_CL45(sc, phy,  in elink_set_preemphasis()
6773 					  phy->rx_preemphasis[i]);  in elink_set_preemphasis()
6778 			CL22_WR_OVER_CL45(sc, phy,  in elink_set_preemphasis()
6781 					  phy->tx_preemphasis[i]);  in elink_set_preemphasis()
6785 static void elink_xgxs_config_init(struct elink_phy *phy,  in elink_xgxs_config_init()  argument
6796 			elink_set_preemphasis(phy, params);  in elink_xgxs_config_init()
6805 			elink_set_autoneg(phy, params, vars, 0);  in elink_xgxs_config_init()
6808 			elink_program_serdes(phy, params, vars);  in elink_xgxs_config_init()
6814 			elink_set_brcm_cl37_advertisement(phy, params);  in elink_xgxs_config_init()
6817 			elink_set_ieee_aneg_advertisement(phy, params,  in elink_xgxs_config_init()
6821 			elink_set_autoneg(phy, params, vars, enable_cl73);  in elink_xgxs_config_init()
6824 			elink_restart_autoneg(phy, params, enable_cl73);  in elink_xgxs_config_init()
6830 		elink_initialize_sgmii_process(phy, params, vars);  in elink_xgxs_config_init()
6834 static elink_status_t elink_prepare_xgxs(struct elink_phy *phy,  in elink_prepare_xgxs()  argument
6840 	if ((phy->req_line_speed &&  in elink_prepare_xgxs()
6841 	     ((phy->req_line_speed == ELINK_SPEED_100) ||  in elink_prepare_xgxs()
6842 	      (phy->req_line_speed == ELINK_SPEED_10))) ||  in elink_prepare_xgxs()
6843 	    (!phy->req_line_speed &&  in elink_prepare_xgxs()
6844 	     (phy->speed_cap_mask >=  in elink_prepare_xgxs()
6846 	     (phy->speed_cap_mask <  in elink_prepare_xgxs()
6848 	    (phy->type == PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT_SD))  in elink_prepare_xgxs()
6853 	elink_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc);  in elink_prepare_xgxs()
6854 	elink_set_aer_mmd(params, phy);  in elink_prepare_xgxs()
6855 	if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT)  in elink_prepare_xgxs()
6856 		elink_set_master_ln(params, phy);  in elink_prepare_xgxs()
6858 	rc = elink_reset_unicore(params, phy, 0);  in elink_prepare_xgxs()
6863 	elink_set_aer_mmd(params, phy);  in elink_prepare_xgxs()
6865 	if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) {  in elink_prepare_xgxs()
6866 		elink_set_master_ln(params, phy);  in elink_prepare_xgxs()
6867 		elink_set_swap_lanes(params, phy);  in elink_prepare_xgxs()
6874 				     struct elink_phy *phy,  in elink_wait_reset_complete()  argument
6880 		if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE)  in elink_wait_reset_complete()
6881 			elink_cl22_read(sc, phy,  in elink_wait_reset_complete()
6884 			elink_cl45_read(sc, phy,  in elink_wait_reset_complete()
6916 			params->phy[ELINK_INT_PHY].type !=  in elink_link_int_enable()
6926 			params->phy[ELINK_INT_PHY].type !=  in elink_link_int_enable()
7082 	spirom_ver = REG_RD(sc, params->phy[ELINK_EXT_PHY1].ver_addr);  in elink_get_ext_phy_fw_version()
7084 	if (params->phy[ELINK_EXT_PHY1].format_fw_ver) {  in elink_get_ext_phy_fw_version()
7085 		status |= params->phy[ELINK_EXT_PHY1].format_fw_ver(spirom_ver,  in elink_get_ext_phy_fw_version()
7091 	    (params->phy[ELINK_EXT_PHY2].ver_addr != 0)) {  in elink_get_ext_phy_fw_version()
7092 		spirom_ver = REG_RD(sc, params->phy[ELINK_EXT_PHY2].ver_addr);  in elink_get_ext_phy_fw_version()
7093 		if (params->phy[ELINK_EXT_PHY2].format_fw_ver) {  in elink_get_ext_phy_fw_version()
7097 			status |= params->phy[ELINK_EXT_PHY2].format_fw_ver(  in elink_get_ext_phy_fw_version()
7108 static void elink_set_xgxs_loopback(struct elink_phy *phy,  in elink_set_xgxs_loopback()  argument
7114 	if (phy->req_line_speed != ELINK_SPEED_1000) {  in elink_set_xgxs_loopback()
7128 		elink_cl45_write(sc, phy,  in elink_set_xgxs_loopback()
7134 		elink_cl45_write(sc, phy,  in elink_set_xgxs_loopback()
7141 		elink_set_aer_mmd(params, phy);  in elink_set_xgxs_loopback()
7151 		elink_cl45_read(sc, phy, 5,  in elink_set_xgxs_loopback()
7155 		elink_cl45_write(sc, phy, 5,  in elink_set_xgxs_loopback()
7178 		if (params->phy[phy_idx].set_link_led) {  in elink_set_led()
7179 			params->phy[phy_idx].set_link_led(  in elink_set_led()
7180 				&params->phy[phy_idx], params, mode);  in elink_set_led()
7197 		if (params->phy[ELINK_EXT_PHY1].type ==  in elink_set_led()
7215 		if (((params->phy[ELINK_EXT_PHY1].type ==  in elink_set_led()
7217 			 (params->phy[ELINK_EXT_PHY1].type ==  in elink_set_led()
7253 		} else if ((params->phy[ELINK_EXT_PHY1].type ==  in elink_set_led()
7323 	struct elink_phy *int_phy = &params->phy[ELINK_INT_PHY];  in elink_test_link()
7373 		ext_phy_link_up = params->phy[ELINK_EXT_PHY1].read_status(  in elink_test_link()
7374 			&params->phy[ELINK_EXT_PHY1],  in elink_test_link()
7380 			serdes_phy_type = ((params->phy[phy_index].media_type ==  in elink_test_link()
7382 					   (params->phy[phy_index].media_type ==  in elink_test_link()
7384 					   (params->phy[phy_index].media_type ==  in elink_test_link()
7386 					   (params->phy[phy_index].media_type ==  in elink_test_link()
7391 			if (params->phy[phy_index].read_status) {  in elink_test_link()
7393 					params->phy[phy_index].read_status(  in elink_test_link()
7394 						&params->phy[phy_index],  in elink_test_link()
7415 	vars->line_speed = params->phy[ELINK_INT_PHY].req_line_speed;  in elink_link_initialize()
7422 		elink_prepare_xgxs(&params->phy[ELINK_INT_PHY], params, vars);  in elink_link_initialize()
7428 	    (params->phy[ELINK_EXT_PHY1].flags & ELINK_FLAGS_INIT_XGXS_FIRST) ||  in elink_link_initialize()
7430 		struct elink_phy *phy = &params->phy[ELINK_INT_PHY];  in elink_link_initialize()  local
7434 			elink_set_parallel_detection(phy, params);  in elink_link_initialize()
7435 		if (params->phy[ELINK_INT_PHY].config_init)  in elink_link_initialize()
7436 			params->phy[ELINK_INT_PHY].config_init(phy, params, vars);  in elink_link_initialize()
7442 	vars->line_speed = params->phy[ELINK_INT_PHY].req_line_speed;  in elink_link_initialize()
7446 		if (params->phy[ELINK_INT_PHY].supported &  in elink_link_initialize()
7457 			if (params->phy[phy_index].supported &  in elink_link_initialize()
7468 			params->phy[phy_index].config_init(  in elink_link_initialize()
7469 				&params->phy[phy_index],  in elink_link_initialize()
7483 static void elink_int_link_reset(struct elink_phy *phy,  in elink_int_link_reset()  argument
7491 static void elink_common_ext_link_reset(struct elink_phy *phy,  in elink_common_ext_link_reset()  argument
7639 		if (params->phy[phy_idx].flags & ELINK_FLAGS_TX_ERROR_CHECK) {  in elink_update_link_up()
7705 		elink_set_aer_mmd(params, &params->phy[ELINK_INT_PHY]);  in elink_link_update()
7733 		struct elink_phy *phy = &params->phy[phy_index];  in elink_link_update()  local
7734 		if (!phy->read_status)  in elink_link_update()
7737 		cur_link_up = phy->read_status(phy, params,  in elink_link_update()
7791 	if (params->phy[ELINK_INT_PHY].read_status)  in elink_link_update()
7792 		params->phy[ELINK_INT_PHY].read_status(  in elink_link_update()
7793 			&params->phy[ELINK_INT_PHY],  in elink_link_update()
7813 			if (params->phy[ELINK_EXT_PHY2].phy_specific_func) {  in elink_link_update()
7816 				params->phy[ELINK_EXT_PHY2].phy_specific_func(  in elink_link_update()
7817 					&params->phy[ELINK_EXT_PHY2],  in elink_link_update()
7824 		if (params->phy[active_external_phy].supported &  in elink_link_update()
7851 		if (params->phy[phy_index].flags &  in elink_link_update()
7899 			   params->phy[ELINK_EXT_PHY1].flags &  in elink_link_update()
7901 		if (!(params->phy[ELINK_EXT_PHY1].flags &  in elink_link_update()
7910 			if (params->phy[ELINK_INT_PHY].config_init)  in elink_link_update()
7911 				params->phy[ELINK_INT_PHY].config_init(  in elink_link_update()
7912 					&params->phy[ELINK_INT_PHY], params,  in elink_link_update()
7974 				      struct elink_phy *phy,  in elink_save_bcm_spirom_ver()  argument
7979 	elink_cl45_read(sc, phy, MDIO_PMA_DEVAD,  in elink_save_bcm_spirom_ver()
7981 	elink_cl45_read(sc, phy, MDIO_PMA_DEVAD,  in elink_save_bcm_spirom_ver()
7984 				  phy->ver_addr);  in elink_save_bcm_spirom_ver()
7988 				       struct elink_phy *phy,  in elink_ext_phy_10G_an_resolve()  argument
7992 	elink_cl45_read(sc, phy,  in elink_ext_phy_10G_an_resolve()
7995 	elink_cl45_read(sc, phy,  in elink_ext_phy_10G_an_resolve()
8007 static void elink_8073_resolve_fc(struct elink_phy *phy,  in elink_8073_resolve_fc()  argument
8012 	if (phy->req_line_speed == ELINK_SPEED_10 ||  in elink_8073_resolve_fc()
8013 	    phy->req_line_speed == ELINK_SPEED_100) {  in elink_8073_resolve_fc()
8014 		vars->flow_ctrl = phy->req_flow_ctrl;  in elink_8073_resolve_fc()
8018 	if (elink_ext_phy_resolve_fc(phy, params, vars) &&  in elink_8073_resolve_fc()
8023 		elink_cl45_read(sc, phy,  in elink_8073_resolve_fc()
8027 		elink_cl45_read(sc, phy,  in elink_8073_resolve_fc()
8035 		elink_pause_resolve(phy, params, vars, pause_result);  in elink_8073_resolve_fc()
8041 					     struct elink_phy *phy,  in elink_8073_8727_external_rom_boot()  argument
8050 	elink_cl45_write(sc, phy,  in elink_8073_8727_external_rom_boot()
8056 	elink_cl45_write(sc, phy,  in elink_8073_8727_external_rom_boot()
8061 	elink_cl45_write(sc, phy,  in elink_8073_8727_external_rom_boot()
8066 	elink_cl45_write(sc, phy,  in elink_8073_8727_external_rom_boot()
8072 	elink_cl45_write(sc, phy,  in elink_8073_8727_external_rom_boot()
8092 		elink_cl45_read(sc, phy,  in elink_8073_8727_external_rom_boot()
8095 		elink_cl45_read(sc, phy,  in elink_8073_8727_external_rom_boot()
8101 			((fw_msgout & 0xff) != 0x03 && (phy->type ==  in elink_8073_8727_external_rom_boot()
8105 	elink_cl45_write(sc, phy,  in elink_8073_8727_external_rom_boot()
8108 	elink_save_bcm_spirom_ver(sc, phy, port);  in elink_8073_8727_external_rom_boot()
8121 static elink_status_t elink_8073_is_snr_needed(struct bxe_softc *sc, struct elink_phy *phy)  in elink_8073_is_snr_needed()  argument
8127 	elink_cl45_read(sc, phy,  in elink_8073_is_snr_needed()
8136 	elink_cl45_read(sc, phy,  in elink_8073_is_snr_needed()
8147 static elink_status_t elink_8073_xaui_wa(struct bxe_softc *sc, struct elink_phy *phy)  in elink_8073_xaui_wa()  argument
8151 	elink_cl45_read(sc, phy,  in elink_8073_xaui_wa()
8166 		elink_cl45_read(sc, phy,  in elink_8073_xaui_wa()
8185 				elink_cl45_read(sc, phy,  in elink_8073_xaui_wa()
8203 static void elink_807x_force_10G(struct bxe_softc *sc, struct elink_phy *phy)  in elink_807x_force_10G()  argument
8206 	elink_cl45_write(sc, phy,  in elink_807x_force_10G()
8208 	elink_cl45_write(sc, phy,  in elink_807x_force_10G()
8210 	elink_cl45_write(sc, phy,  in elink_807x_force_10G()
8212 	elink_cl45_write(sc, phy,  in elink_807x_force_10G()
8217 				      struct elink_phy *phy,  in elink_8073_set_pause_cl37()  argument
8222 	elink_cl45_read(sc, phy,  in elink_8073_set_pause_cl37()
8227 	elink_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc);  in elink_8073_set_pause_cl37()
8246 	elink_cl45_write(sc, phy,  in elink_8073_set_pause_cl37()
8251 static void elink_8073_specific_func(struct elink_phy *phy,  in elink_8073_specific_func()  argument
8259 		elink_cl45_write(sc, phy,  in elink_8073_specific_func()
8261 		elink_cl45_write(sc, phy,  in elink_8073_specific_func()
8267 static elink_status_t elink_8073_config_init(struct elink_phy *phy,  in elink_8073_config_init()  argument
8287 	elink_8073_specific_func(phy, params, ELINK_PHY_INIT);  in elink_8073_config_init()
8288 	elink_8073_set_pause_cl37(params, phy, vars);  in elink_8073_config_init()
8290 	elink_cl45_read(sc, phy,  in elink_8073_config_init()
8293 	elink_cl45_read(sc, phy,  in elink_8073_config_init()
8303 		elink_cl45_read(sc, phy,  in elink_8073_config_init()
8306 		elink_cl45_write(sc, phy,  in elink_8073_config_init()
8319 		elink_cl45_read(sc, phy,  in elink_8073_config_init()
8322 		elink_cl45_write(sc, phy,  in elink_8073_config_init()
8328 		elink_807x_force_10G(sc, phy);  in elink_8073_config_init()
8332 		elink_cl45_write(sc, phy,  in elink_8073_config_init()
8335 	if (phy->req_line_speed != ELINK_SPEED_AUTO_NEG) {  in elink_8073_config_init()
8336 		if (phy->req_line_speed == ELINK_SPEED_10000) {  in elink_8073_config_init()
8338 		} else if (phy->req_line_speed ==  ELINK_SPEED_2500) {  in elink_8073_config_init()
8347 		if (phy->speed_cap_mask &  in elink_8073_config_init()
8352 		if (phy->speed_cap_mask &  in elink_8073_config_init()
8359 	elink_cl45_write(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV, val);  in elink_8073_config_init()
8360 	elink_cl45_read(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_8073_2_5G, &tmp1);  in elink_8073_config_init()
8362 	if (((phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G) &&  in elink_8073_config_init()
8363 	     (phy->req_line_speed == ELINK_SPEED_AUTO_NEG)) ||  in elink_8073_config_init()
8364 	    (phy->req_line_speed == ELINK_SPEED_2500)) {  in elink_8073_config_init()
8367 		elink_cl45_read(sc, phy,  in elink_8073_config_init()
8380 	elink_cl45_write(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_8073_2_5G, tmp1);  in elink_8073_config_init()
8383 	elink_cl45_read(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, &tmp1);  in elink_8073_config_init()
8384 	elink_cl45_write(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD,  in elink_8073_config_init()
8385 			 (tmp1 | ((phy->req_duplex == DUPLEX_FULL) ?  in elink_8073_config_init()
8389 	elink_cl45_write(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1000);  in elink_8073_config_init()
8395 	if (elink_8073_is_snr_needed(sc, phy))  in elink_8073_config_init()
8396 		elink_cl45_write(sc, phy,  in elink_8073_config_init()
8401 	elink_cl45_read(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV2, &tmp1);  in elink_8073_config_init()
8403 	elink_cl45_write(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV2, tmp1);  in elink_8073_config_init()
8405 	elink_ext_phy_set_pause(params, phy, vars);  in elink_8073_config_init()
8409 	elink_cl45_write(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x1200);  in elink_8073_config_init()
8415 static uint8_t elink_8073_read_status(struct elink_phy *phy,  in elink_8073_read_status()  argument
8425 	elink_cl45_read(sc, phy,  in elink_8073_read_status()
8431 	elink_cl45_read(sc, phy,  in elink_8073_read_status()
8433 	elink_cl45_read(sc, phy,  in elink_8073_read_status()
8437 	elink_cl45_read(sc, phy,  in elink_8073_read_status()
8441 	elink_cl45_read(sc, phy,  in elink_8073_read_status()
8447 	elink_cl45_read(sc, phy,  in elink_8073_read_status()
8451 	elink_cl45_read(sc, phy,  in elink_8073_read_status()
8453 	elink_cl45_read(sc, phy,  in elink_8073_read_status()
8459 	     ((phy->req_line_speed != ELINK_SPEED_10000))) {  in elink_8073_read_status()
8460 		if (elink_8073_xaui_wa(sc, phy) != 0)  in elink_8073_read_status()
8463 	elink_cl45_read(sc, phy,  in elink_8073_read_status()
8465 	elink_cl45_read(sc, phy,  in elink_8073_read_status()
8469 	elink_cl45_read(sc, phy,  in elink_8073_read_status()
8471 	elink_cl45_read(sc, phy,  in elink_8073_read_status()
8477 	if (link_up && elink_8073_is_snr_needed(sc, phy)) {  in elink_8073_read_status()
8482 		elink_cl45_write(sc, phy,  in elink_8073_read_status()
8487 		elink_cl45_write(sc, phy,  in elink_8073_read_status()
8491 	elink_cl45_read(sc, phy,  in elink_8073_read_status()
8522 			elink_cl45_read(sc, phy,  in elink_8073_read_status()
8535 			elink_cl45_write(sc, phy,  in elink_8073_read_status()
8540 		elink_ext_phy_10G_an_resolve(sc, phy, vars);  in elink_8073_read_status()
8541 		elink_8073_resolve_fc(phy, params, vars);  in elink_8073_read_status()
8546 		elink_cl45_read(sc, phy, MDIO_AN_DEVAD,  in elink_8073_read_status()
8560 static void elink_8073_link_reset(struct elink_phy *phy,  in elink_8073_link_reset()  argument
8579 static elink_status_t elink_8705_config_init(struct elink_phy *phy,  in elink_8705_config_init()  argument
8590 	elink_cl45_write(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0xa040);  in elink_8705_config_init()
8591 	elink_wait_reset_complete(sc, phy, params);  in elink_8705_config_init()
8593 	elink_cl45_write(sc, phy,  in elink_8705_config_init()
8595 	elink_cl45_write(sc, phy,  in elink_8705_config_init()
8597 	elink_cl45_write(sc, phy,  in elink_8705_config_init()
8599 	elink_cl45_write(sc, phy,  in elink_8705_config_init()
8606 static uint8_t elink_8705_read_status(struct elink_phy *phy,  in elink_8705_read_status()  argument
8614 	elink_cl45_read(sc, phy,  in elink_8705_read_status()
8618 	elink_cl45_read(sc, phy,  in elink_8705_read_status()
8622 	elink_cl45_read(sc, phy,  in elink_8705_read_status()
8625 	elink_cl45_read(sc, phy,  in elink_8705_read_status()
8627 	elink_cl45_read(sc, phy,  in elink_8705_read_status()
8634 		elink_ext_phy_resolve_fc(phy, params, vars);  in elink_8705_read_status()
8643 					   struct elink_phy *phy,  in elink_set_disable_pmd_transmit()  argument
8660 	elink_cl45_write(sc, phy,  in elink_set_disable_pmd_transmit()
8680 					   struct elink_phy *phy,  in elink_sfp_e1e2_set_transmitter()  argument
8698 		elink_cl45_read(sc, phy,  in elink_sfp_e1e2_set_transmitter()
8708 		elink_cl45_write(sc, phy,  in elink_sfp_e1e2_set_transmitter()
8737 				      struct elink_phy *phy,  in elink_sfp_set_transmitter()  argument
8743 		elink_sfp_e3_set_transmitter(params, phy, tx_en);  in elink_sfp_set_transmitter()
8745 		elink_sfp_e1e2_set_transmitter(params, phy, tx_en);  in elink_sfp_set_transmitter()
8748 static elink_status_t elink_8726_read_sfp_module_eeprom(struct elink_phy *phy,  in elink_8726_read_sfp_module_eeprom()  argument
8762 	elink_cl45_write(sc, phy,  in elink_8726_read_sfp_module_eeprom()
8767 	elink_cl45_write(sc, phy,  in elink_8726_read_sfp_module_eeprom()
8772 	elink_cl45_write(sc, phy,  in elink_8726_read_sfp_module_eeprom()
8778 		elink_cl45_read(sc, phy,  in elink_8726_read_sfp_module_eeprom()
8797 		elink_cl45_read(sc, phy,  in elink_8726_read_sfp_module_eeprom()
8804 		elink_cl45_read(sc, phy,  in elink_8726_read_sfp_module_eeprom()
8836 static elink_status_t elink_warpcore_read_sfp_module_eeprom(struct elink_phy *phy,  in elink_warpcore_read_sfp_module_eeprom()  argument
8879 static elink_status_t elink_8727_read_sfp_module_eeprom(struct elink_phy *phy,  in elink_8727_read_sfp_module_eeprom()  argument
8897 	elink_cl45_write(sc, phy,  in elink_8727_read_sfp_module_eeprom()
8903 	elink_cl45_read(sc, phy,  in elink_8727_read_sfp_module_eeprom()
8909 	elink_cl45_write(sc, phy,  in elink_8727_read_sfp_module_eeprom()
8915 	elink_cl45_write(sc, phy,  in elink_8727_read_sfp_module_eeprom()
8920 	elink_cl45_write(sc, phy,  in elink_8727_read_sfp_module_eeprom()
8926 	elink_cl45_write(sc, phy,  in elink_8727_read_sfp_module_eeprom()
8937 		elink_cl45_read(sc, phy,  in elink_8727_read_sfp_module_eeprom()
8956 		elink_cl45_read(sc, phy,  in elink_8727_read_sfp_module_eeprom()
8963 		elink_cl45_read(sc, phy,  in elink_8727_read_sfp_module_eeprom()
8974 elink_status_t elink_read_sfp_module_eeprom(struct elink_phy *phy,  in elink_read_sfp_module_eeprom()  argument
8988 	switch (phy->type) {  in elink_read_sfp_module_eeprom()
9006 		rc = read_func(phy, params, dev_addr, addr, xfer_size,  in elink_read_sfp_module_eeprom()
9015 static elink_status_t elink_get_edc_mode(struct elink_phy *phy,  in elink_get_edc_mode()  argument
9023 	phy->media_type = ELINK_ETH_PHY_UNSPECIFIED;  in elink_get_edc_mode()
9025 	if (elink_read_sfp_module_eeprom(phy,  in elink_get_edc_mode()
9042 		phy->media_type = ELINK_ETH_PHY_DA_TWINAX;  in elink_get_edc_mode()
9050 			if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT)  in elink_get_edc_mode()
9084 			phy->media_type = ELINK_ETH_PHY_SFP_1G_FIBER;  in elink_get_edc_mode()
9085 			if (phy->req_line_speed != ELINK_SPEED_1000) {  in elink_get_edc_mode()
9087 				phy->req_line_speed = ELINK_SPEED_1000;  in elink_get_edc_mode()
9103 				elink_sfp_set_transmitter(params, phy, 0);  in elink_get_edc_mode()
9105 				elink_sfp_set_transmitter(params, phy, 1);  in elink_get_edc_mode()
9111 				if (params->phy[idx].type == phy->type) {  in elink_get_edc_mode()
9116 			phy->media_type = ELINK_ETH_PHY_SFPP_10G_FIBER;  in elink_get_edc_mode()
9117 			phy->req_line_speed = params->req_line_speed[cfg_idx];  in elink_get_edc_mode()
9131 		if (&(params->phy[phy_idx]) == phy) {  in elink_get_edc_mode()
9134 			media_types |= ((phy->media_type &  in elink_get_edc_mode()
9143 		if (elink_read_sfp_module_eeprom(phy,  in elink_get_edc_mode()
9164 static elink_status_t elink_verify_sfp_module(struct elink_phy *phy,  in elink_verify_sfp_module()  argument
9172 	phy->flags &= ~ELINK_FLAGS_SFP_NOT_APPROVED;  in elink_verify_sfp_module()
9202 	fw_cmd_param = ELINK_FW_PARAM_SET(phy->addr, phy->type, phy->mdio_ctrl);  in elink_verify_sfp_module()
9210 	if (elink_read_sfp_module_eeprom(phy,  in elink_verify_sfp_module()
9219 	if (elink_read_sfp_module_eeprom(phy,  in elink_verify_sfp_module()
9234 		phy->flags |= ELINK_FLAGS_SFP_NOT_APPROVED;  in elink_verify_sfp_module()
9238 static elink_status_t elink_wait_for_sfp_module_initialized(struct elink_phy *phy,  in elink_wait_for_sfp_module_initialized()  argument
9251 		if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT)  in elink_wait_for_sfp_module_initialized()
9253 				phy, params, ELINK_I2C_DEV_ADDR_A0, 1, 1, &val,  in elink_wait_for_sfp_module_initialized()
9256 			rc = elink_read_sfp_module_eeprom(phy, params,  in elink_wait_for_sfp_module_initialized()
9267 	rc = elink_read_sfp_module_eeprom(phy, params, ELINK_I2C_DEV_ADDR_A0,  in elink_wait_for_sfp_module_initialized()
9273 				    struct elink_phy *phy,  in elink_8727_power_module()  argument
9288 	if (phy->flags & ELINK_FLAGS_NOC)  in elink_8727_power_module()
9298 	elink_cl45_write(sc, phy,  in elink_8727_power_module()
9305 					struct elink_phy *phy,  in elink_8726_set_limiting_mode()  argument
9310 	elink_cl45_read(sc, phy,  in elink_8726_set_limiting_mode()
9319 		elink_cl45_write(sc, phy,  in elink_8726_set_limiting_mode()
9333 		elink_cl45_write(sc, phy,  in elink_8726_set_limiting_mode()
9337 		elink_cl45_write(sc, phy,  in elink_8726_set_limiting_mode()
9341 		elink_cl45_write(sc, phy,  in elink_8726_set_limiting_mode()
9345 		elink_cl45_write(sc, phy,  in elink_8726_set_limiting_mode()
9354 					struct elink_phy *phy,  in elink_8727_set_limiting_mode()  argument
9359 	elink_cl45_read(sc, phy,  in elink_8727_set_limiting_mode()
9364 	elink_cl45_write(sc, phy,  in elink_8727_set_limiting_mode()
9369 	elink_cl45_read(sc, phy,  in elink_8727_set_limiting_mode()
9374 	elink_cl45_write(sc, phy,  in elink_8727_set_limiting_mode()
9379 	elink_cl45_write(sc, phy,  in elink_8727_set_limiting_mode()
9387 static void elink_8727_specific_func(struct elink_phy *phy,  in elink_8727_specific_func()  argument
9395 		elink_sfp_set_transmitter(params, phy, 0);  in elink_8727_specific_func()
9398 		if (!(phy->flags & ELINK_FLAGS_SFP_NOT_APPROVED))  in elink_8727_specific_func()
9399 			elink_sfp_set_transmitter(params, phy, 1);  in elink_8727_specific_func()
9402 		elink_cl45_write(sc, phy,  in elink_8727_specific_func()
9405 		elink_cl45_write(sc, phy,  in elink_8727_specific_func()
9408 		elink_cl45_write(sc, phy,  in elink_8727_specific_func()
9411 		elink_cl45_read(sc, phy, MDIO_PMA_DEVAD,  in elink_8727_specific_func()
9415 		if (phy->flags & ELINK_FLAGS_NOC)  in elink_8727_specific_func()
9420 		if (!(phy->flags & ELINK_FLAGS_NOC))  in elink_8727_specific_func()
9422 		elink_cl45_write(sc, phy,  in elink_8727_specific_func()
9495 static void elink_warpcore_hw_reset(struct elink_phy *phy,  in elink_warpcore_hw_reset()  argument
9510 				   struct elink_phy *phy,  in elink_power_sfp_module()  argument
9516 	switch (phy->type) {  in elink_power_sfp_module()
9519 		elink_8727_power_module(params->sc, phy, power);  in elink_power_sfp_module()
9529 					     struct elink_phy *phy,  in elink_warpcore_set_limiting_mode()  argument
9536 	uint8_t lane = elink_get_warpcore_lane(phy, params);  in elink_warpcore_set_limiting_mode()
9538 	elink_cl45_read(sc, phy, MDIO_WC_DEVAD,  in elink_warpcore_set_limiting_mode()
9556 	elink_cl45_write(sc, phy, MDIO_WC_DEVAD,  in elink_warpcore_set_limiting_mode()
9559 	elink_cl45_read(sc, phy, MDIO_WC_DEVAD,  in elink_warpcore_set_limiting_mode()
9563 	elink_warpcore_reset_lane(sc, phy, 1);  in elink_warpcore_set_limiting_mode()
9564 	elink_warpcore_reset_lane(sc, phy, 0);  in elink_warpcore_set_limiting_mode()
9569 				    struct elink_phy *phy,  in elink_set_limiting_mode()  argument
9572 	switch (phy->type) {  in elink_set_limiting_mode()
9574 		elink_8726_set_limiting_mode(params->sc, phy, edc_mode);  in elink_set_limiting_mode()
9578 		elink_8727_set_limiting_mode(params->sc, phy, edc_mode);  in elink_set_limiting_mode()
9581 		elink_warpcore_set_limiting_mode(params, phy, edc_mode);  in elink_set_limiting_mode()
9586 elink_status_t elink_sfp_module_detection(struct elink_phy *phy,  in elink_sfp_module_detection()  argument
9597 	elink_sfp_set_transmitter(params, phy, 1);  in elink_sfp_module_detection()
9601 	elink_power_sfp_module(params, phy, 1);  in elink_sfp_module_detection()
9602 	if (elink_get_edc_mode(phy, params, &edc_mode) != 0) {  in elink_sfp_module_detection()
9605 	} else if (elink_verify_sfp_module(phy, params) != 0) {  in elink_sfp_module_detection()
9617 			elink_power_sfp_module(params, phy, 0);  in elink_sfp_module_detection()
9628 	elink_set_limiting_mode(params, phy, edc_mode);  in elink_sfp_module_detection()
9636 		elink_sfp_set_transmitter(params, phy, 0);  in elink_sfp_module_detection()
9644 	struct elink_phy *phy;  in elink_handle_module_detect_int()  local
9648 		phy = &params->phy[ELINK_INT_PHY];  in elink_handle_module_detect_int()
9650 		elink_sfp_set_transmitter(params, phy, 1);  in elink_handle_module_detect_int()
9652 		phy = &params->phy[ELINK_EXT_PHY1];  in elink_handle_module_detect_int()
9670 		elink_set_aer_mmd(params, phy);  in elink_handle_module_detect_int()
9672 		elink_power_sfp_module(params, phy, 1);  in elink_handle_module_detect_int()
9676 		if (elink_wait_for_sfp_module_initialized(phy, params) == 0) {  in elink_handle_module_detect_int()
9677 			elink_sfp_module_detection(phy, params);  in elink_handle_module_detect_int()
9684 				elink_cl45_read(sc, phy,  in elink_handle_module_detect_int()
9691 					elink_warpcore_reset_lane(sc, phy, 1);  in elink_handle_module_detect_int()
9692 					elink_warpcore_config_sfi(phy, params);  in elink_handle_module_detect_int()
9693 					elink_warpcore_reset_lane(sc, phy, 0);  in elink_handle_module_detect_int()
9706 		phy->media_type = ELINK_ETH_PHY_NOT_PRESENT;  in elink_handle_module_detect_int()
9714 				 struct elink_phy *phy,  in elink_sfp_mask_fault()  argument
9719 	elink_cl45_read(sc, phy,  in elink_sfp_mask_fault()
9722 	elink_cl45_read(sc, phy,  in elink_sfp_mask_fault()
9726 	elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, alarm_ctrl_offset, &val);  in elink_sfp_mask_fault()
9731 	elink_cl45_write(sc, phy, MDIO_PMA_DEVAD, alarm_ctrl_offset, val);  in elink_sfp_mask_fault()
9736 static uint8_t elink_8706_8726_read_status(struct elink_phy *phy,  in elink_8706_8726_read_status()  argument
9745 	elink_cl45_read(sc, phy,  in elink_8706_8726_read_status()
9748 	elink_sfp_mask_fault(sc, phy, MDIO_PMA_LASI_TXSTAT,  in elink_8706_8726_read_status()
9752 	elink_cl45_read(sc, phy,  in elink_8706_8726_read_status()
9754 	elink_cl45_read(sc, phy,  in elink_8706_8726_read_status()
9758 	elink_cl45_read(sc, phy,  in elink_8706_8726_read_status()
9760 	elink_cl45_read(sc, phy,  in elink_8706_8726_read_status()
9762 	elink_cl45_read(sc, phy,  in elink_8706_8726_read_status()
9764 	elink_cl45_read(sc, phy,  in elink_8706_8726_read_status()
9778 		elink_ext_phy_resolve_fc(phy, params, vars);  in elink_8706_8726_read_status()
9784 		elink_cl45_read(sc, phy, MDIO_PMA_DEVAD,  in elink_8706_8726_read_status()
9786 		elink_cl45_read(sc, phy, MDIO_PMA_DEVAD,  in elink_8706_8726_read_status()
9798 static uint8_t elink_8706_config_init(struct elink_phy *phy,  in elink_8706_config_init()  argument
9810 	elink_cl45_write(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0xa040);  in elink_8706_config_init()
9811 	elink_wait_reset_complete(sc, phy, params);  in elink_8706_config_init()
9815 		elink_cl45_read(sc, phy,  in elink_8706_config_init()
9830 			elink_cl45_read(sc, phy, MDIO_XS_DEVAD, reg, &val);  in elink_8706_config_init()
9834 			val |= (phy->rx_preemphasis[i] & 0x7);  in elink_8706_config_init()
9837 			elink_cl45_write(sc, phy, MDIO_XS_DEVAD, reg, val);  in elink_8706_config_init()
9841 	if (phy->req_line_speed == ELINK_SPEED_10000) {  in elink_8706_config_init()
9844 		elink_cl45_write(sc, phy,  in elink_8706_config_init()
9847 		elink_cl45_write(sc, phy,  in elink_8706_config_init()
9851 		elink_cl45_write(sc, phy,  in elink_8706_config_init()
9858 		elink_cl45_write(sc, phy,  in elink_8706_config_init()
9862 		elink_cl45_write(sc, phy,  in elink_8706_config_init()
9865 		elink_cl45_write(sc, phy,  in elink_8706_config_init()
9868 		elink_cl45_write(sc, phy,  in elink_8706_config_init()
9872 		elink_cl45_write(sc, phy,  in elink_8706_config_init()
9874 		elink_cl45_write(sc, phy,  in elink_8706_config_init()
9877 		elink_cl45_write(sc, phy,  in elink_8706_config_init()
9881 	elink_save_bcm_spirom_ver(sc, phy, params->port);  in elink_8706_config_init()
9894 		elink_cl45_read(sc, phy,  in elink_8706_config_init()
9897 		elink_cl45_write(sc, phy,  in elink_8706_config_init()
9904 static elink_status_t elink_8706_read_status(struct elink_phy *phy,  in elink_8706_read_status()  argument
9908 	return elink_8706_8726_read_status(phy, params, vars);  in elink_8706_read_status()
9914 static void elink_8726_config_loopback(struct elink_phy *phy,  in elink_8726_config_loopback()  argument
9919 	elink_cl45_write(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x0001);  in elink_8726_config_loopback()
9922 static void elink_8726_external_rom_boot(struct elink_phy *phy,  in elink_8726_external_rom_boot()  argument
9930 	elink_cl45_write(sc, phy,  in elink_8726_external_rom_boot()
9934 	elink_cl45_write(sc, phy,  in elink_8726_external_rom_boot()
9939 	elink_cl45_write(sc, phy,  in elink_8726_external_rom_boot()
9943 	elink_cl45_write(sc, phy,  in elink_8726_external_rom_boot()
9952 	elink_cl45_write(sc, phy,  in elink_8726_external_rom_boot()
9957 	elink_save_bcm_spirom_ver(sc, phy, params->port);  in elink_8726_external_rom_boot()
9960 static uint8_t elink_8726_read_status(struct elink_phy *phy,  in elink_8726_read_status()  argument
9966 	uint8_t link_up = elink_8706_8726_read_status(phy, params, vars);  in elink_8726_read_status()
9968 		elink_cl45_read(sc, phy,  in elink_8726_read_status()
9981 static elink_status_t elink_8726_config_init(struct elink_phy *phy,  in elink_8726_config_init()  argument
9988 	elink_cl45_write(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1<<15);  in elink_8726_config_init()
9989 	elink_wait_reset_complete(sc, phy, params);  in elink_8726_config_init()
9991 	elink_8726_external_rom_boot(phy, params);  in elink_8726_config_init()
9998 	elink_sfp_module_detection(phy, params);  in elink_8726_config_init()
10000 	if (phy->req_line_speed == ELINK_SPEED_1000) {  in elink_8726_config_init()
10002 		elink_cl45_write(sc, phy,  in elink_8726_config_init()
10004 		elink_cl45_write(sc, phy,  in elink_8726_config_init()
10006 		elink_cl45_write(sc, phy,  in elink_8726_config_init()
10008 		elink_cl45_write(sc, phy,  in elink_8726_config_init()
10011 	} else if ((phy->req_line_speed == ELINK_SPEED_AUTO_NEG) &&  in elink_8726_config_init()
10012 		   (phy->speed_cap_mask &  in elink_8726_config_init()
10014 		   ((phy->speed_cap_mask &  in elink_8726_config_init()
10019 		elink_ext_phy_set_pause(params, phy, vars);  in elink_8726_config_init()
10020 		elink_cl45_write(sc, phy,  in elink_8726_config_init()
10022 		elink_cl45_write(sc, phy,  in elink_8726_config_init()
10024 		elink_cl45_write(sc, phy,  in elink_8726_config_init()
10026 		elink_cl45_write(sc, phy,  in elink_8726_config_init()
10028 		elink_cl45_write(sc, phy,  in elink_8726_config_init()
10033 		elink_cl45_write(sc, phy,  in elink_8726_config_init()
10035 		elink_cl45_write(sc, phy,  in elink_8726_config_init()
10040 		elink_cl45_write(sc, phy,  in elink_8726_config_init()
10049 			 phy->tx_preemphasis[0],  in elink_8726_config_init()
10050 			 phy->tx_preemphasis[1]);  in elink_8726_config_init()
10051 		elink_cl45_write(sc, phy,  in elink_8726_config_init()
10054 				 phy->tx_preemphasis[0]);  in elink_8726_config_init()
10056 		elink_cl45_write(sc, phy,  in elink_8726_config_init()
10059 				 phy->tx_preemphasis[1]);  in elink_8726_config_init()
10066 static void elink_8726_link_reset(struct elink_phy *phy,  in elink_8726_link_reset()  argument
10072 	elink_cl45_write(sc, phy,  in elink_8726_link_reset()
10081 static void elink_8727_set_link_led(struct elink_phy *phy,  in elink_8727_set_link_led()  argument
10089 	if (!(phy->flags & ELINK_FLAGS_NOC))  in elink_8727_set_link_led()
10106 	elink_cl45_read(sc, phy,  in elink_8727_set_link_led()
10112 	elink_cl45_write(sc, phy,  in elink_8727_set_link_led()
10116 	elink_cl45_read(sc, phy,  in elink_8727_set_link_led()
10122 	elink_cl45_write(sc, phy,  in elink_8727_set_link_led()
10127 static void elink_8727_hw_reset(struct elink_phy *phy,  in elink_8727_hw_reset()  argument
10142 static void elink_8727_config_speed(struct elink_phy *phy,  in elink_8727_config_speed()  argument
10148 	if ((phy->req_line_speed == ELINK_SPEED_1000) ||  in elink_8727_config_speed()
10149 	    (phy->media_type == ELINK_ETH_PHY_SFP_1G_FIBER)) {  in elink_8727_config_speed()
10151 		elink_cl45_write(sc, phy,  in elink_8727_config_speed()
10153 		elink_cl45_write(sc, phy,  in elink_8727_config_speed()
10155 		elink_cl45_read(sc, phy,  in elink_8727_config_speed()
10162 			elink_cl45_read(sc, phy,  in elink_8727_config_speed()
10166 			elink_cl45_write(sc, phy,  in elink_8727_config_speed()
10170 	} else if ((phy->req_line_speed == ELINK_SPEED_AUTO_NEG) &&  in elink_8727_config_speed()
10171 		   ((phy->speed_cap_mask &  in elink_8727_config_speed()
10173 		   ((phy->speed_cap_mask &  in elink_8727_config_speed()
10178 		elink_cl45_write(sc, phy,  in elink_8727_config_speed()
10180 		elink_cl45_write(sc, phy,  in elink_8727_config_speed()
10186 		elink_cl45_write(sc, phy,  in elink_8727_config_speed()
10189 		elink_cl45_write(sc, phy,  in elink_8727_config_speed()
10191 		elink_cl45_write(sc, phy,  in elink_8727_config_speed()
10193 		elink_cl45_write(sc, phy,  in elink_8727_config_speed()
10199 static elink_status_t elink_8727_config_init(struct elink_phy *phy,  in elink_8727_config_init()  argument
10208 	elink_wait_reset_complete(sc, phy, params);  in elink_8727_config_init()
10212 	elink_8727_specific_func(phy, params, ELINK_PHY_INIT);  in elink_8727_config_init()
10216 	elink_cl45_read(sc, phy,  in elink_8727_config_init()
10223 	if (!(phy->flags & ELINK_FLAGS_NOC))  in elink_8727_config_init()
10225 	elink_cl45_write(sc, phy,  in elink_8727_config_init()
10229 	elink_set_disable_pmd_transmit(params, phy, 0);  in elink_8727_config_init()
10231 	elink_8727_power_module(sc, phy, 1);  in elink_8727_config_init()
10233 	elink_cl45_read(sc, phy,  in elink_8727_config_init()
10236 	elink_cl45_read(sc, phy,  in elink_8727_config_init()
10239 	elink_8727_config_speed(phy, params);  in elink_8727_config_init()
10246 			   phy->tx_preemphasis[0],  in elink_8727_config_init()
10247 			   phy->tx_preemphasis[1]);  in elink_8727_config_init()
10248 		elink_cl45_write(sc, phy,  in elink_8727_config_init()
10250 				 phy->tx_preemphasis[0]);  in elink_8727_config_init()
10252 		elink_cl45_write(sc, phy,  in elink_8727_config_init()
10254 				 phy->tx_preemphasis[1]);  in elink_8727_config_init()
10268 		elink_cl45_read(sc, phy,  in elink_8727_config_init()
10272 		elink_cl45_write(sc, phy,  in elink_8727_config_init()
10274 		elink_cl45_read(sc, phy,  in elink_8727_config_init()
10277 		elink_cl45_write(sc, phy,  in elink_8727_config_init()
10285 static void elink_8727_handle_mod_abs(struct elink_phy *phy,  in elink_8727_handle_mod_abs()  argument
10294 	elink_cl45_read(sc, phy,  in elink_8727_handle_mod_abs()
10302 		phy->media_type = ELINK_ETH_PHY_NOT_PRESENT;  in elink_8727_handle_mod_abs()
10311 		if (!(phy->flags & ELINK_FLAGS_NOC))  in elink_8727_handle_mod_abs()
10313 		elink_cl45_write(sc, phy,  in elink_8727_handle_mod_abs()
10320 		elink_cl45_read(sc, phy,  in elink_8727_handle_mod_abs()
10336 		if (!(phy->flags & ELINK_FLAGS_NOC))  in elink_8727_handle_mod_abs()
10338 		elink_cl45_write(sc, phy,  in elink_8727_handle_mod_abs()
10347 		elink_cl45_read(sc, phy,  in elink_8727_handle_mod_abs()
10354 			elink_sfp_set_transmitter(params, phy, 0);  in elink_8727_handle_mod_abs()
10356 		if (elink_wait_for_sfp_module_initialized(phy, params) == 0)  in elink_8727_handle_mod_abs()
10357 			elink_sfp_module_detection(phy, params);  in elink_8727_handle_mod_abs()
10362 		elink_8727_config_speed(phy, params);  in elink_8727_handle_mod_abs()
10370 static uint8_t elink_8727_read_status(struct elink_phy *phy,  in elink_8727_read_status()  argument
10381 	elink_cl45_read(sc, phy,  in elink_8727_read_status()
10388 	elink_cl45_read(sc, phy,  in elink_8727_read_status()
10394 	elink_sfp_mask_fault(sc, phy, MDIO_PMA_LASI_TXSTAT,  in elink_8727_read_status()
10397 	elink_cl45_read(sc, phy,  in elink_8727_read_status()
10403 	elink_cl45_read(sc, phy,  in elink_8727_read_status()
10409 	if (!(phy->flags & ELINK_FLAGS_NOC) && !(rx_alarm_status & (1<<5))) {  in elink_8727_read_status()
10411 		elink_cl45_read(sc, phy,  in elink_8727_read_status()
10430 			elink_cl45_write(sc, phy,  in elink_8727_read_status()
10434 			elink_cl45_read(sc, phy,  in elink_8727_read_status()
10439 			elink_cl45_write(sc, phy,  in elink_8727_read_status()
10443 			elink_cl45_read(sc, phy,  in elink_8727_read_status()
10446 			elink_8727_power_module(params->sc, phy, 0);  in elink_8727_read_status()
10453 		elink_8727_handle_mod_abs(phy, params);  in elink_8727_read_status()
10455 		elink_cl45_write(sc, phy,  in elink_8727_read_status()
10460 	if (!(phy->flags & ELINK_FLAGS_SFP_NOT_APPROVED)) {  in elink_8727_read_status()
10462 		elink_sfp_set_transmitter(params, phy, 1);  in elink_8727_read_status()
10468 	elink_cl45_read(sc, phy,  in elink_8727_read_status()
10493 		elink_cl45_read(sc, phy, MDIO_PMA_DEVAD,  in elink_8727_read_status()
10496 		elink_cl45_read(sc, phy, MDIO_PMA_DEVAD,  in elink_8727_read_status()
10505 		elink_ext_phy_resolve_fc(phy, params, vars);  in elink_8727_read_status()
10511 	    (phy->req_line_speed == ELINK_SPEED_1000)) {  in elink_8727_read_status()
10512 		elink_cl45_read(sc, phy,  in elink_8727_read_status()
10522 		elink_cl45_write(sc, phy,  in elink_8727_read_status()
10529 static void elink_8727_link_reset(struct elink_phy *phy,  in elink_8727_link_reset()  argument
10535 	elink_set_disable_pmd_transmit(params, phy, 1);  in elink_8727_link_reset()
10538 	elink_sfp_set_transmitter(params, phy, 0);  in elink_8727_link_reset()
10540 	elink_cl45_write(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0);  in elink_8727_link_reset()
10547 static int elink_is_8483x_8485x(struct elink_phy *phy)  in elink_is_8483x_8485x()  argument
10549 	return ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) ||  in elink_is_8483x_8485x()
10550 		(phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834) ||  in elink_is_8483x_8485x()
10551 		(phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84858));  in elink_is_8483x_8485x()
10554 static void elink_save_848xx_spirom_version(struct elink_phy *phy,  in elink_save_848xx_spirom_version()  argument
10568 	if (elink_is_8483x_8485x(phy)) {  in elink_save_848xx_spirom_version()
10569 		elink_cl45_read(sc, phy, MDIO_CTL_DEVAD, 0x400f, &fw_ver1);  in elink_save_848xx_spirom_version()
10571 				phy->ver_addr);  in elink_save_848xx_spirom_version()
10576 			elink_cl45_write(sc, phy, reg_set[i].devad,  in elink_save_848xx_spirom_version()
10580 			elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, 0xA818, &val);  in elink_save_848xx_spirom_version()
10589 						  phy->ver_addr);  in elink_save_848xx_spirom_version()
10595 		elink_cl45_write(sc, phy, MDIO_PMA_DEVAD, 0xA819, 0x0000);  in elink_save_848xx_spirom_version()
10596 		elink_cl45_write(sc, phy, MDIO_PMA_DEVAD, 0xA81A, 0xc200);  in elink_save_848xx_spirom_version()
10597 		elink_cl45_write(sc, phy, MDIO_PMA_DEVAD, 0xA817, 0x000A);  in elink_save_848xx_spirom_version()
10599 			elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, 0xA818, &val);  in elink_save_848xx_spirom_version()
10608 						  phy->ver_addr);  in elink_save_848xx_spirom_version()
10613 		elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, 0xA81B, &fw_ver1);  in elink_save_848xx_spirom_version()
10615 		elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, 0xA81C, &fw_ver2);  in elink_save_848xx_spirom_version()
10618 					  phy->ver_addr);  in elink_save_848xx_spirom_version()
10623 				struct elink_phy *phy)  in elink_848xx_set_led()  argument
10636 	elink_cl45_read(sc, phy,  in elink_848xx_set_led()
10642 	elink_cl45_write(sc, phy,  in elink_848xx_set_led()
10647 		elink_cl45_write(sc, phy, reg_set[i].devad, reg_set[i].reg,  in elink_848xx_set_led()
10650 	if (elink_is_8483x_8485x(phy))  in elink_848xx_set_led()
10656 	elink_cl45_read_or_write(sc, phy,  in elink_848xx_set_led()
10661 static void elink_848xx_specific_func(struct elink_phy *phy,  in elink_848xx_specific_func()  argument
10668 		if (!elink_is_8483x_8485x(phy)) {  in elink_848xx_specific_func()
10670 			elink_save_848xx_spirom_version(phy, sc, params->port);  in elink_848xx_specific_func()
10679 		elink_848xx_set_led(sc, phy);  in elink_848xx_specific_func()
10684 static elink_status_t elink_848xx_cmn_config_init(struct elink_phy *phy,  in elink_848xx_cmn_config_init()  argument
10691 	elink_848xx_specific_func(phy, params, ELINK_PHY_INIT);  in elink_848xx_cmn_config_init()
10692 	elink_cl45_write(sc, phy,  in elink_848xx_cmn_config_init()
10696 	elink_cl45_read(sc, phy,  in elink_848xx_cmn_config_init()
10700 	elink_ext_phy_set_pause(params, phy, vars);  in elink_848xx_cmn_config_init()
10701 	elink_cl45_read(sc, phy,  in elink_848xx_cmn_config_init()
10705 	elink_cl45_read(sc, phy,  in elink_848xx_cmn_config_init()
10712 	if (((phy->req_line_speed == ELINK_SPEED_AUTO_NEG) &&  in elink_848xx_cmn_config_init()
10713 	     (phy->speed_cap_mask &  in elink_848xx_cmn_config_init()
10715 	    (phy->req_line_speed == ELINK_SPEED_1000)) {  in elink_848xx_cmn_config_init()
10718 		if (phy->req_duplex == DUPLEX_FULL)  in elink_848xx_cmn_config_init()
10724 	elink_cl45_write(sc, phy,  in elink_848xx_cmn_config_init()
10729 	if (phy->req_line_speed == ELINK_SPEED_AUTO_NEG) {  in elink_848xx_cmn_config_init()
10730 		if (phy->speed_cap_mask &  in elink_848xx_cmn_config_init()
10739 		if (phy->speed_cap_mask &  in elink_848xx_cmn_config_init()
10748 		if ((phy->speed_cap_mask &  in elink_848xx_cmn_config_init()
10750 		    (phy->supported & ELINK_SUPPORTED_10baseT_Full)) {  in elink_848xx_cmn_config_init()
10756 		if ((phy->speed_cap_mask &  in elink_848xx_cmn_config_init()
10758 		    (phy->supported & ELINK_SUPPORTED_10baseT_Half)) {  in elink_848xx_cmn_config_init()
10766 	if ((phy->req_line_speed == ELINK_SPEED_100) &&  in elink_848xx_cmn_config_init()
10767 	    (phy->supported &  in elink_848xx_cmn_config_init()
10772 		elink_cl45_write(sc, phy,  in elink_848xx_cmn_config_init()
10779 	if ((phy->req_line_speed == ELINK_SPEED_10) &&  in elink_848xx_cmn_config_init()
10780 	    (phy->supported &  in elink_848xx_cmn_config_init()
10784 		elink_cl45_write(sc, phy,  in elink_848xx_cmn_config_init()
10790 	elink_cl45_write(sc, phy,  in elink_848xx_cmn_config_init()
10794 	if (phy->req_duplex == DUPLEX_FULL)  in elink_848xx_cmn_config_init()
10800 	if (!elink_is_8483x_8485x(phy) ||  in elink_848xx_cmn_config_init()
10802 		elink_cl45_write(sc, phy,  in elink_848xx_cmn_config_init()
10806 	if (((phy->req_line_speed == ELINK_SPEED_AUTO_NEG) &&  in elink_848xx_cmn_config_init()
10807 	    (phy->speed_cap_mask &  in elink_848xx_cmn_config_init()
10809 		(phy->req_line_speed == ELINK_SPEED_10000)) {  in elink_848xx_cmn_config_init()
10814 				sc, phy,  in elink_848xx_cmn_config_init()
10818 			elink_cl45_write(sc, phy,  in elink_848xx_cmn_config_init()
10822 		elink_cl45_write(sc, phy,  in elink_848xx_cmn_config_init()
10830 static elink_status_t elink_8481_config_init(struct elink_phy *phy,  in elink_8481_config_init()  argument
10841 	elink_wait_reset_complete(sc, phy, params);  in elink_8481_config_init()
10843 	elink_cl45_write(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1<<15);  in elink_8481_config_init()
10844 	return elink_848xx_cmn_config_init(phy, params, vars);  in elink_8481_config_init()
10850 static elink_status_t elink_84858_cmd_hdlr(struct elink_phy *phy,  in elink_84858_cmd_hdlr()  argument
10867 		elink_cl45_read(sc, phy, MDIO_CTL_DEVAD,  in elink_84858_cmd_hdlr()
10884 		elink_cl45_write(sc, phy, MDIO_CTL_DEVAD,  in elink_84858_cmd_hdlr()
10892 	elink_cl45_write(sc, phy, MDIO_CTL_DEVAD,  in elink_84858_cmd_hdlr()
10901 		elink_cl45_read(sc, phy, MDIO_CTL_DEVAD,  in elink_84858_cmd_hdlr()
10919 		elink_cl45_read(sc, phy, MDIO_CTL_DEVAD,  in elink_84858_cmd_hdlr()
10927 static elink_status_t elink_84833_cmd_hdlr(struct elink_phy *phy,  in elink_84833_cmd_hdlr()  argument
10938 	elink_cl45_write(sc, phy, MDIO_CTL_DEVAD,  in elink_84833_cmd_hdlr()
10944 		elink_cl45_read(sc, phy, MDIO_CTL_DEVAD,  in elink_84833_cmd_hdlr()
10957 			elink_cl45_write(sc, phy, MDIO_CTL_DEVAD,  in elink_84833_cmd_hdlr()
10967 		elink_cl45_write(sc, phy, MDIO_CTL_DEVAD,  in elink_84833_cmd_hdlr()
10974 	elink_cl45_write(sc, phy, MDIO_CTL_DEVAD,  in elink_84833_cmd_hdlr()
10977 		elink_cl45_read(sc, phy, MDIO_CTL_DEVAD,  in elink_84833_cmd_hdlr()
10992 		elink_cl45_read(sc, phy, MDIO_CTL_DEVAD,  in elink_84833_cmd_hdlr()
10999 	elink_cl45_write(sc, phy, MDIO_CTL_DEVAD,  in elink_84833_cmd_hdlr()
11006 static elink_status_t elink_848xx_cmd_hdlr(struct elink_phy *phy,  in elink_848xx_cmd_hdlr()  argument
11014 	if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84858) ||  in elink_848xx_cmd_hdlr()
11018 		return elink_84858_cmd_hdlr(phy, params, fw_cmd, cmd_args,  in elink_848xx_cmd_hdlr()
11021 		return elink_84833_cmd_hdlr(phy, params, fw_cmd, cmd_args,  in elink_848xx_cmd_hdlr()
11026 static elink_status_t elink_848xx_pair_swap_cfg(struct elink_phy *phy,  in elink_848xx_pair_swap_cfg()  argument
11047 	status = elink_848xx_cmd_hdlr(phy, params,  in elink_848xx_pair_swap_cfg()
11094 static elink_status_t elink_84833_hw_reset_phy(struct elink_phy *phy,  in elink_84833_hw_reset_phy()  argument
11106 	elink_cl45_write(sc, phy, MDIO_AN_DEVAD,  in elink_84833_hw_reset_phy()
11109 	elink_cl45_write(sc, phy, MDIO_AN_DEVAD,  in elink_84833_hw_reset_phy()
11127 static elink_status_t elink_8483x_disable_eee(struct elink_phy *phy,  in elink_8483x_disable_eee()  argument
11138 	rc = elink_848xx_cmd_hdlr(phy, params, PHY848xx_CMD_SET_EEE_MODE,  in elink_8483x_disable_eee()
11145 	return elink_eee_disable(phy, params, vars);  in elink_8483x_disable_eee()
11148 static elink_status_t elink_8483x_enable_eee(struct elink_phy *phy,  in elink_8483x_enable_eee()  argument
11156 	rc = elink_848xx_cmd_hdlr(phy, params, PHY848xx_CMD_SET_EEE_MODE,  in elink_8483x_enable_eee()
11163 	return elink_eee_advertise(phy, params, vars, SHMEM_EEE_10G_ADV);  in elink_8483x_enable_eee()
11167 static elink_status_t elink_848x3_config_init(struct elink_phy *phy,  in elink_848x3_config_init()  argument
11185 	if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823) {  in elink_848x3_config_init()
11191 		elink_cl45_write(sc, phy,  in elink_848x3_config_init()
11196 	elink_wait_reset_complete(sc, phy, params);  in elink_848x3_config_init()
11200 	if (!elink_is_8483x_8485x(phy)) {  in elink_848x3_config_init()
11207 		elink_set_autoneg(&params->phy[ELINK_INT_PHY], params, vars, 0);  in elink_848x3_config_init()
11208 		elink_program_serdes(&params->phy[ELINK_INT_PHY], params, vars);  in elink_848x3_config_init()
11212 	if (phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84858) {  in elink_848x3_config_init()
11215 		elink_cl45_read(sc, phy, MDIO_AN_DEVAD,  in elink_848x3_config_init()
11224 	elink_cl45_read(sc, phy, MDIO_CTL_DEVAD,  in elink_848x3_config_init()
11260 	if (params->phy[ELINK_EXT_PHY2].req_line_speed == ELINK_SPEED_1000)  in elink_848x3_config_init()
11263 	elink_cl45_write(sc, phy, MDIO_CTL_DEVAD,  in elink_848x3_config_init()
11268 	if (elink_is_8483x_8485x(phy)) {  in elink_848x3_config_init()
11269 		elink_848xx_pair_swap_cfg(phy, params, vars);  in elink_848x3_config_init()
11276 		rc = elink_848xx_cmd_hdlr(phy, params,  in elink_848x3_config_init()
11283 		rc = elink_848xx_cmn_config_init(phy, params, vars);  in elink_848x3_config_init()
11285 		elink_save_848xx_spirom_version(phy, sc, params->port);  in elink_848x3_config_init()
11287 	if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823) {  in elink_848x3_config_init()
11293 		elink_cl45_read(sc, phy, MDIO_CTL_DEVAD,  in elink_848x3_config_init()
11299 		elink_cl45_write(sc, phy, MDIO_CTL_DEVAD,  in elink_848x3_config_init()
11303 	elink_cl45_read(sc, phy, MDIO_CTL_DEVAD,  in elink_848x3_config_init()
11313 			elink_8483x_disable_eee(phy, params, vars);  in elink_848x3_config_init()
11317 		if ((phy->req_duplex == DUPLEX_FULL) &&  in elink_848x3_config_init()
11321 			rc = elink_8483x_enable_eee(phy, params, vars);  in elink_848x3_config_init()
11323 			rc = elink_8483x_disable_eee(phy, params, vars);  in elink_848x3_config_init()
11332 	if (elink_is_8483x_8485x(phy)) {  in elink_848x3_config_init()
11334 		elink_cl45_read_and_write(sc, phy,  in elink_848x3_config_init()
11342 static uint8_t elink_848xx_read_status(struct elink_phy *phy,  in elink_848xx_read_status()  argument
11353 	elink_cl45_read(sc, phy,  in elink_848xx_read_status()
11355 	elink_cl45_read(sc, phy,  in elink_848xx_read_status()
11365 		elink_ext_phy_10G_an_resolve(sc, phy, vars);  in elink_848xx_read_status()
11370 		elink_cl45_write(sc, phy,  in elink_848xx_read_status()
11375 		elink_cl45_read(sc, phy,  in elink_848xx_read_status()
11399 			elink_cl45_read(sc, phy,  in elink_848xx_read_status()
11418 			elink_cl45_read(sc, phy,  in elink_848xx_read_status()
11425 			elink_cl45_read(sc, phy,  in elink_848xx_read_status()
11437 		elink_ext_phy_resolve_fc(phy, params, vars);  in elink_848xx_read_status()
11440 		elink_cl45_read(sc, phy, MDIO_AN_DEVAD,  in elink_848xx_read_status()
11458 		elink_cl45_read(sc, phy, MDIO_AN_DEVAD,  in elink_848xx_read_status()
11468 		elink_cl45_read(sc, phy, MDIO_AN_DEVAD,  in elink_848xx_read_status()
11476 		if (elink_is_8483x_8485x(phy))  in elink_848xx_read_status()
11477 			elink_eee_an_resolve(phy, params, vars);  in elink_848xx_read_status()
11492 static void elink_8481_hw_reset(struct elink_phy *phy,  in elink_8481_hw_reset()  argument
11501 static void elink_8481_link_reset(struct elink_phy *phy,  in elink_8481_link_reset()  argument
11504 	elink_cl45_write(params->sc, phy,  in elink_8481_link_reset()
11506 	elink_cl45_write(params->sc, phy,  in elink_8481_link_reset()
11510 static void elink_848x3_link_reset(struct elink_phy *phy,  in elink_848x3_link_reset()  argument
11522 	if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823) {  in elink_848x3_link_reset()
11527 		elink_cl45_read(sc, phy,  in elink_848x3_link_reset()
11531 		elink_cl45_write(sc, phy,  in elink_848x3_link_reset()
11537 static void elink_848xx_set_link_led(struct elink_phy *phy,  in elink_848xx_set_link_led()  argument
11557 			elink_cl45_write(sc, phy,  in elink_848xx_set_link_led()
11562 			elink_cl45_write(sc, phy,  in elink_848xx_set_link_led()
11567 			elink_cl45_write(sc, phy,  in elink_848xx_set_link_led()
11572 			elink_cl45_write(sc, phy,  in elink_848xx_set_link_led()
11578 			elink_cl45_write(sc, phy,  in elink_848xx_set_link_led()
11593 			elink_cl45_write(sc, phy,  in elink_848xx_set_link_led()
11598 			elink_cl45_write(sc, phy,  in elink_848xx_set_link_led()
11603 			elink_cl45_write(sc, phy,  in elink_848xx_set_link_led()
11608 			elink_cl45_write(sc, phy,  in elink_848xx_set_link_led()
11614 			elink_cl45_write(sc, phy,  in elink_848xx_set_link_led()
11618 			if (phy->type ==  in elink_848xx_set_link_led()
11635 				elink_cl45_write(sc, phy,  in elink_848xx_set_link_led()
11649 			elink_cl45_read(sc, phy,  in elink_848xx_set_link_led()
11656 			elink_cl45_write(sc, phy,  in elink_848xx_set_link_led()
11662 			elink_cl45_write(sc, phy,  in elink_848xx_set_link_led()
11667 			elink_cl45_write(sc, phy,  in elink_848xx_set_link_led()
11672 			elink_cl45_write(sc, phy,  in elink_848xx_set_link_led()
11677 			elink_cl45_write(sc, phy,  in elink_848xx_set_link_led()
11682 			elink_cl45_write(sc, phy,  in elink_848xx_set_link_led()
11686 			if (phy->type ==  in elink_848xx_set_link_led()
11703 				elink_cl45_write(sc, phy,  in elink_848xx_set_link_led()
11719 			elink_cl45_read(sc, phy,  in elink_848xx_set_link_led()
11728 				elink_cl45_write(sc, phy,  in elink_848xx_set_link_led()
11735 			elink_cl45_write(sc, phy,  in elink_848xx_set_link_led()
11740 			elink_cl45_write(sc, phy,  in elink_848xx_set_link_led()
11745 			elink_cl45_write(sc, phy,  in elink_848xx_set_link_led()
11750 			elink_cl45_write(sc, phy,  in elink_848xx_set_link_led()
11764 			elink_cl45_write(sc, phy,  in elink_848xx_set_link_led()
11770 			elink_cl45_read(sc, phy,  in elink_848xx_set_link_led()
11776 			elink_cl45_write(sc, phy,  in elink_848xx_set_link_led()
11780 			if (phy->type ==  in elink_848xx_set_link_led()
11785 				elink_cl45_write(sc, phy,  in elink_848xx_set_link_led()
11804 		elink_cl45_read(sc, phy, MDIO_WC_DEVAD,  in elink_848xx_set_link_led()
11812 static void elink_54618se_specific_func(struct elink_phy *phy,  in elink_54618se_specific_func()  argument
11822 		elink_cl22_write(sc, phy,  in elink_54618se_specific_func()
11825 		elink_cl22_read(sc, phy,  in elink_54618se_specific_func()
11830 		elink_cl22_write(sc, phy,  in elink_54618se_specific_func()
11834 		elink_cl22_write(sc, phy,  in elink_54618se_specific_func()
11841 static elink_status_t elink_54618se_config_init(struct elink_phy *phy,  in elink_54618se_config_init()  argument
11871 	elink_cl22_write(sc, phy,  in elink_54618se_config_init()
11873 	elink_wait_reset_complete(sc, phy, params);  in elink_54618se_config_init()
11879 	elink_54618se_specific_func(phy, params, ELINK_PHY_INIT);  in elink_54618se_config_init()
11881 	elink_cl22_write(sc, phy,  in elink_54618se_config_init()
11884 	elink_cl22_read(sc, phy,  in elink_54618se_config_init()
11888 	elink_cl22_write(sc, phy,  in elink_54618se_config_init()
11894 	elink_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc);  in elink_54618se_config_init()
11905 	elink_cl22_read(sc, phy,  in elink_54618se_config_init()
11909 	elink_cl22_read(sc, phy,  in elink_54618se_config_init()
11913 	elink_cl22_read(sc, phy,  in elink_54618se_config_init()
11922 	if (((phy->req_line_speed == ELINK_SPEED_AUTO_NEG) &&  in elink_54618se_config_init()
11923 			(phy->speed_cap_mask &  in elink_54618se_config_init()
11925 			(phy->req_line_speed == ELINK_SPEED_1000)) {  in elink_54618se_config_init()
11928 		if (phy->req_duplex == DUPLEX_FULL)  in elink_54618se_config_init()
11934 	elink_cl22_write(sc, phy,  in elink_54618se_config_init()
11937 	elink_cl22_read(sc, phy,  in elink_54618se_config_init()
11942 	if (phy->req_line_speed == ELINK_SPEED_AUTO_NEG) {  in elink_54618se_config_init()
11943 		if (phy->speed_cap_mask &  in elink_54618se_config_init()
11949 		if (phy->speed_cap_mask &  in elink_54618se_config_init()
11955 		if (phy->speed_cap_mask &  in elink_54618se_config_init()
11961 		if (phy->speed_cap_mask &  in elink_54618se_config_init()
11970 	if (phy->req_line_speed == ELINK_SPEED_100) {  in elink_54618se_config_init()
11973 		elink_cl22_write(sc, phy,  in elink_54618se_config_init()
11978 	if (phy->req_line_speed == ELINK_SPEED_10) {  in elink_54618se_config_init()
11980 		elink_cl22_write(sc, phy,  in elink_54618se_config_init()
11986 	if ((phy->flags & ELINK_FLAGS_EEE) && elink_eee_has_cap(params)) {  in elink_54618se_config_init()
11989 		elink_cl22_write(sc, phy, MDIO_REG_GPHY_EXP_ACCESS,  in elink_54618se_config_init()
11992 		elink_cl22_read(sc, phy, MDIO_REG_GPHY_EXP_ACCESS_GATE, &temp);  in elink_54618se_config_init()
11994 		elink_cl22_write(sc, phy, MDIO_REG_GPHY_EXP_ACCESS_GATE, temp);  in elink_54618se_config_init()
11999 			elink_eee_disable(phy, params, vars);  in elink_54618se_config_init()
12001 			   (phy->req_duplex == DUPLEX_FULL) &&  in elink_54618se_config_init()
12009 			elink_eee_advertise(phy, params, vars,  in elink_54618se_config_init()
12013 			elink_eee_disable(phy, params, vars);  in elink_54618se_config_init()
12019 		if (phy->flags & ELINK_FLAGS_EEE) {  in elink_54618se_config_init()
12029 			elink_cl45_write(sc, phy, MDIO_AN_DEVAD,  in elink_54618se_config_init()
12034 	elink_cl22_write(sc, phy,  in elink_54618se_config_init()
12038 	if (phy->req_duplex == DUPLEX_FULL)  in elink_54618se_config_init()
12041 	elink_cl22_write(sc, phy,  in elink_54618se_config_init()
12048 static void elink_5461x_set_link_led(struct elink_phy *phy,  in elink_5461x_set_link_led()  argument
12054 	elink_cl22_write(sc, phy,  in elink_5461x_set_link_led()
12057 	elink_cl22_read(sc, phy,  in elink_5461x_set_link_led()
12077 	elink_cl22_write(sc, phy,  in elink_5461x_set_link_led()
12084 static void elink_54618se_link_reset(struct elink_phy *phy,  in elink_54618se_link_reset()  argument
12094 	elink_cl22_write(sc, phy, MDIO_PMA_REG_CTRL, 0x800);  in elink_54618se_link_reset()
12109 static uint8_t elink_54618se_read_status(struct elink_phy *phy,  in elink_54618se_read_status()  argument
12119 	elink_cl22_read(sc, phy,  in elink_54618se_read_status()
12125 	elink_cl22_read(sc, phy,  in elink_54618se_read_status()
12162 		elink_cl22_read(sc, phy,  in elink_54618se_read_status()
12168 		elink_cl22_read(sc, phy,  in elink_54618se_read_status()
12178 		elink_ext_phy_resolve_fc(phy, params, vars);  in elink_54618se_read_status()
12182 			elink_cl22_read(sc, phy, 0x5, &val);  in elink_54618se_read_status()
12200 			elink_cl22_read(sc, phy, 0xa, &val);  in elink_54618se_read_status()
12208 			if ((phy->flags & ELINK_FLAGS_EEE) &&  in elink_54618se_read_status()
12210 				elink_eee_an_resolve(phy, params, vars);  in elink_54618se_read_status()
12216 static void elink_54618se_config_loopback(struct elink_phy *phy,  in elink_54618se_config_loopback()  argument
12227 	elink_cl22_write(sc, phy, 0x09, 3<<11);  in elink_54618se_config_loopback()
12234 	elink_cl22_read(sc, phy, 0x00, &val);  in elink_54618se_config_loopback()
12237 	elink_cl22_write(sc, phy, 0x00, val);  in elink_54618se_config_loopback()
12243 	elink_cl22_write(sc, phy, 0x18, 7);  in elink_54618se_config_loopback()
12244 	elink_cl22_read(sc, phy, 0x18, &val);  in elink_54618se_config_loopback()
12245 	elink_cl22_write(sc, phy, 0x18, val | (1<<10) | (1<<15));  in elink_54618se_config_loopback()
12259 static void elink_7101_config_loopback(struct elink_phy *phy,  in elink_7101_config_loopback()  argument
12264 	elink_cl45_write(sc, phy,  in elink_7101_config_loopback()
12268 static elink_status_t elink_7101_config_init(struct elink_phy *phy,  in elink_7101_config_init()  argument
12281 	elink_wait_reset_complete(sc, phy, params);  in elink_7101_config_init()
12283 	elink_cl45_write(sc, phy,  in elink_7101_config_init()
12286 	elink_cl45_write(sc, phy,  in elink_7101_config_init()
12289 	elink_ext_phy_set_pause(params, phy, vars);  in elink_7101_config_init()
12291 	elink_cl45_read(sc, phy,  in elink_7101_config_init()
12294 	elink_cl45_write(sc, phy,  in elink_7101_config_init()
12298 	elink_cl45_read(sc, phy,  in elink_7101_config_init()
12301 	elink_cl45_read(sc, phy,  in elink_7101_config_init()
12304 				  (uint32_t)(fw_ver1<<16 | fw_ver2), phy->ver_addr);  in elink_7101_config_init()
12308 static uint8_t elink_7101_read_status(struct elink_phy *phy,  in elink_7101_read_status()  argument
12315 	elink_cl45_read(sc, phy,  in elink_7101_read_status()
12317 	elink_cl45_read(sc, phy,  in elink_7101_read_status()
12321 	elink_cl45_read(sc, phy,  in elink_7101_read_status()
12323 	elink_cl45_read(sc, phy,  in elink_7101_read_status()
12330 		elink_cl45_read(sc, phy,  in elink_7101_read_status()
12337 		elink_ext_phy_10G_an_resolve(sc, phy, vars);  in elink_7101_read_status()
12338 		elink_ext_phy_resolve_fc(phy, params, vars);  in elink_7101_read_status()
12361 void elink_sfx7101_sp_sw_reset(struct bxe_softc *sc, struct elink_phy *phy)  in elink_sfx7101_sp_sw_reset()  argument
12365 	elink_cl45_read(sc, phy,  in elink_sfx7101_sp_sw_reset()
12372 		elink_cl45_write(sc, phy,  in elink_sfx7101_sp_sw_reset()
12377 		elink_cl45_read(sc, phy,  in elink_sfx7101_sp_sw_reset()
12386 static void elink_7101_hw_reset(struct elink_phy *phy,  in elink_7101_hw_reset()  argument
12396 static void elink_7101_set_link_led(struct elink_phy *phy,  in elink_7101_set_link_led()  argument
12413 	elink_cl45_write(sc, phy,  in elink_7101_set_link_led()
12957 				     struct elink_phy *phy, uint8_t port,  in elink_populate_preemphasis()  argument
12985 		phy->rx_preemphasis[i << 1] = ((rx>>16) & 0xffff);  in elink_populate_preemphasis()
12986 		phy->rx_preemphasis[(i << 1) + 1] = (rx & 0xffff);  in elink_populate_preemphasis()
12988 		phy->tx_preemphasis[i << 1] = ((tx>>16) & 0xffff);  in elink_populate_preemphasis()
12989 		phy->tx_preemphasis[(i << 1) + 1] = (tx & 0xffff);  in elink_populate_preemphasis()
12991 			phy->rx_preemphasis[i << 1], phy->tx_preemphasis[i << 1]);  in elink_populate_preemphasis()
13018 				  struct elink_phy *phy)  in elink_populate_int_phy()  argument
13034 		*phy = phy_warpcore;  in elink_populate_int_phy()
13036 			phy->flags |= ELINK_FLAGS_4_PORT_MODE;  in elink_populate_int_phy()
13038 			phy->flags &= ~ELINK_FLAGS_4_PORT_MODE;  in elink_populate_int_phy()
13049 			phy->supported &= (ELINK_SUPPORTED_10baseT_Half |  in elink_populate_int_phy()
13058 			phy->media_type = ELINK_ETH_PHY_BASE_T;  in elink_populate_int_phy()
13061 			phy->supported &= (ELINK_SUPPORTED_1000baseT_Full |  in elink_populate_int_phy()
13066 			phy->media_type = ELINK_ETH_PHY_XFP_FIBER;  in elink_populate_int_phy()
13069 			phy->supported &= (ELINK_SUPPORTED_1000baseT_Full |  in elink_populate_int_phy()
13074 			phy->media_type = ELINK_ETH_PHY_SFPP_10G_FIBER;  in elink_populate_int_phy()
13077 			phy->media_type = ELINK_ETH_PHY_KR;  in elink_populate_int_phy()
13078 			phy->supported &= (ELINK_SUPPORTED_1000baseKX_Full |  in elink_populate_int_phy()
13086 			phy->media_type = ELINK_ETH_PHY_KR;  in elink_populate_int_phy()
13087 			phy->flags |= ELINK_FLAGS_WC_DUAL_MODE;  in elink_populate_int_phy()
13088 			phy->supported &= (ELINK_SUPPORTED_20000baseMLD2_Full |  in elink_populate_int_phy()
13094 			phy->media_type = ELINK_ETH_PHY_KR;  in elink_populate_int_phy()
13095 			phy->flags |= ELINK_FLAGS_WC_DUAL_MODE;  in elink_populate_int_phy()
13096 			phy->supported &= (ELINK_SUPPORTED_20000baseKR2_Full |  in elink_populate_int_phy()
13103 			phy->flags &= ~ELINK_FLAGS_TX_ERROR_CHECK;  in elink_populate_int_phy()
13116 			phy->flags |= ELINK_FLAGS_MDC_MDIO_WA;  in elink_populate_int_phy()
13118 			phy->flags |= ELINK_FLAGS_MDC_MDIO_WA_B0;  in elink_populate_int_phy()
13120 				phy->media_type, phy->flags, phy->supported);  in elink_populate_int_phy()
13128 			*phy = phy_serdes;  in elink_populate_int_phy()
13134 			*phy = phy_xgxs;  in elink_populate_int_phy()
13141 	phy->addr = (uint8_t)phy_addr;  in elink_populate_int_phy()
13142 	phy->mdio_ctrl = elink_get_emac_base(sc,  in elink_populate_int_phy()
13146 		phy->def_md_devad = ELINK_E2_DEFAULT_PHY_DEV_ADDR;  in elink_populate_int_phy()
13148 		phy->def_md_devad = ELINK_DEFAULT_PHY_DEV_ADDR;  in elink_populate_int_phy()
13151 		   port, phy->addr, phy->mdio_ctrl);  in elink_populate_int_phy()
13153 	elink_populate_preemphasis(sc, shmem_base, phy, port, ELINK_INT_PHY);  in elink_populate_int_phy()
13162 				  struct elink_phy *phy)  in elink_populate_ext_phy()  argument
13173 		*phy = phy_8073;  in elink_populate_ext_phy()
13176 		*phy = phy_8705;  in elink_populate_ext_phy()
13179 		*phy = phy_8706;  in elink_populate_ext_phy()
13183 		*phy = phy_8726;  in elink_populate_ext_phy()
13188 		*phy = phy_8727;  in elink_populate_ext_phy()
13189 		phy->flags |= ELINK_FLAGS_NOC;  in elink_populate_ext_phy()
13194 		*phy = phy_8727;  in elink_populate_ext_phy()
13197 		*phy = phy_8481;  in elink_populate_ext_phy()
13200 		*phy = phy_84823;  in elink_populate_ext_phy()
13203 		*phy = phy_84833;  in elink_populate_ext_phy()
13206 		*phy = phy_84834;  in elink_populate_ext_phy()
13209 		*phy = phy_84858;  in elink_populate_ext_phy()
13213 		*phy = phy_54618se;  in elink_populate_ext_phy()
13215 			phy->flags |= ELINK_FLAGS_EEE;  in elink_populate_ext_phy()
13218 		*phy = phy_7101;  in elink_populate_ext_phy()
13221 		*phy = phy_null;  in elink_populate_ext_phy()
13224 		*phy = phy_null;  in elink_populate_ext_phy()
13232 	phy->addr = ELINK_XGXS_EXT_PHY_ADDR(ext_phy_config);  in elink_populate_ext_phy()
13233 	elink_populate_preemphasis(sc, shmem_base, phy, port, phy_index);  in elink_populate_ext_phy()
13242 		phy->ver_addr = shmem_base + offsetof(struct shmem_region,  in elink_populate_ext_phy()
13254 			phy->ver_addr = shmem2_base +  in elink_populate_ext_phy()
13265 	phy->mdio_ctrl = elink_get_emac_base(sc, mdc_mdio_access, port);  in elink_populate_ext_phy()
13267 	if (elink_is_8483x_8485x(phy) && (phy->ver_addr)) {  in elink_populate_ext_phy()
13271 		uint32_t raw_ver = REG_RD(sc, phy->ver_addr);  in elink_populate_ext_phy()
13274 			phy->supported &= ~(ELINK_SUPPORTED_100baseT_Half |  in elink_populate_ext_phy()
13281 		   phy->addr, phy->mdio_ctrl);  in elink_populate_ext_phy()
13286 			      uint32_t shmem2_base, uint8_t port, struct elink_phy *phy)  in elink_populate_phy()  argument
13289 	phy->type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN;  in elink_populate_phy()
13291 		return elink_populate_int_phy(sc, shmem_base, port, phy);  in elink_populate_phy()
13293 					port, phy);  in elink_populate_phy()
13298 			      struct elink_phy *phy,  in elink_phy_def_cfg()  argument
13308 		phy->speed_cap_mask = REG_RD(sc, params->shmem_base +  in elink_phy_def_cfg()
13316 		phy->speed_cap_mask = REG_RD(sc, params->shmem_base +  in elink_phy_def_cfg()
13323 	   phy_index, link_config, phy->speed_cap_mask);  in elink_phy_def_cfg()
13325 	phy->req_duplex = DUPLEX_FULL;  in elink_phy_def_cfg()
13328 		phy->req_duplex = DUPLEX_HALF;  in elink_phy_def_cfg()
13330 		phy->req_line_speed = ELINK_SPEED_10;  in elink_phy_def_cfg()
13333 		phy->req_duplex = DUPLEX_HALF;  in elink_phy_def_cfg()
13335 		phy->req_line_speed = ELINK_SPEED_100;  in elink_phy_def_cfg()
13338 		phy->req_line_speed = ELINK_SPEED_1000;  in elink_phy_def_cfg()
13341 		phy->req_line_speed = ELINK_SPEED_2500;  in elink_phy_def_cfg()
13344 		phy->req_line_speed = ELINK_SPEED_10000;  in elink_phy_def_cfg()
13347 		phy->req_line_speed = ELINK_SPEED_AUTO_NEG;  in elink_phy_def_cfg()
13352 			phy_index, phy->req_duplex);  in elink_phy_def_cfg()
13356 		phy->req_flow_ctrl = ELINK_FLOW_CTRL_AUTO;  in elink_phy_def_cfg()
13359 		phy->req_flow_ctrl = ELINK_FLOW_CTRL_TX;  in elink_phy_def_cfg()
13362 		phy->req_flow_ctrl = ELINK_FLOW_CTRL_RX;  in elink_phy_def_cfg()
13365 		phy->req_flow_ctrl = ELINK_FLOW_CTRL_BOTH;  in elink_phy_def_cfg()
13368 		phy->req_flow_ctrl = ELINK_FLOW_CTRL_NONE;  in elink_phy_def_cfg()
13372 			phy->req_duplex, phy->req_line_speed, phy->req_flow_ctrl);  in elink_phy_def_cfg()
13412 	struct elink_phy *phy;  in elink_phy_probe()  local
13434 		phy = &params->phy[actual_phy_idx];  in elink_phy_probe()
13437 				       phy) != ELINK_STATUS_OK) {  in elink_phy_probe()
13444 				*phy = phy_null;  in elink_phy_probe()
13447 		if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN)  in elink_phy_probe()
13452 			phy->flags &= ~ELINK_FLAGS_TX_ERROR_CHECK;  in elink_phy_probe()
13456 			phy->flags |= ELINK_FLAGS_MDC_MDIO_WA_G;  in elink_phy_probe()
13470 			media_types |= ((phy->media_type &  in elink_phy_probe()
13477 		elink_phy_def_cfg(params, phy, phy_index);  in elink_phy_probe()
13724 	elink_set_aer_mmd(params, &params->phy[0]);  in elink_init_xmac_loopback()
13725 	elink_warpcore_reset_lane(sc, &params->phy[0], 0);  in elink_init_xmac_loopback()
13726 	params->phy[ELINK_INT_PHY].config_loopback(  in elink_init_xmac_loopback()
13727 			&params->phy[ELINK_INT_PHY],  in elink_init_xmac_loopback()
13753 	struct elink_phy *int_phy = &params->phy[ELINK_INT_PHY];  in elink_init_xgxs_loopback()
13791 			if (params->phy[phy_index].config_loopback)  in elink_init_xgxs_loopback()
13792 				params->phy[phy_index].config_loopback(  in elink_init_xgxs_loopback()
13793 					&params->phy[phy_index],  in elink_init_xgxs_loopback()
13836 		struct elink_phy *phy = &params->phy[phy_idx];  in elink_avoid_link_flap()  local
13837 		if (phy->phy_specific_func) {  in elink_avoid_link_flap()
13839 			phy->phy_specific_func(phy, params, ELINK_PHY_INIT);  in elink_avoid_link_flap()
13841 		if ((phy->media_type == ELINK_ETH_PHY_SFPP_10G_FIBER) ||  in elink_avoid_link_flap()
13842 		    (phy->media_type == ELINK_ETH_PHY_SFP_1G_FIBER) ||  in elink_avoid_link_flap()
13843 		    (phy->media_type == ELINK_ETH_PHY_DA_TWINAX))  in elink_avoid_link_flap()
13844 			elink_verify_sfp_module(phy, params);  in elink_avoid_link_flap()
14130 			if (params->phy[phy_index].link_reset) {  in elink_link_reset()
14132 						  &params->phy[phy_index]);  in elink_link_reset()
14133 				params->phy[phy_index].link_reset(  in elink_link_reset()
14134 					&params->phy[phy_index],  in elink_link_reset()
14137 			if (params->phy[phy_index].flags &  in elink_link_reset()
14152 	if (params->phy[ELINK_INT_PHY].link_reset)  in elink_link_reset()
14153 		params->phy[ELINK_INT_PHY].link_reset(  in elink_link_reset()
14154 			&params->phy[ELINK_INT_PHY], params);  in elink_link_reset()
14235 	struct elink_phy phy[PORT_MAX];  in elink_8073_common_init_phy()  local
14261 				       port_of_path, &phy[port]) !=  in elink_8073_common_init_phy()
14282 		elink_cl45_write(sc, &phy[port],  in elink_8073_common_init_phy()
14291 	if (phy[PORT_0].addr & 0x1) {  in elink_8073_common_init_phy()
14292 		phy_blk[PORT_0] = &(phy[PORT_1]);  in elink_8073_common_init_phy()
14293 		phy_blk[PORT_1] = &(phy[PORT_0]);  in elink_8073_common_init_phy()
14295 		phy_blk[PORT_0] = &(phy[PORT_0]);  in elink_8073_common_init_phy()
14296 		phy_blk[PORT_1] = &(phy[PORT_1]);  in elink_8073_common_init_phy()
14363 	struct elink_phy phy;  in elink_8726_common_init_phy()  local
14386 				       port, &phy) !=  in elink_8726_common_init_phy()
14393 		elink_cl45_write(sc, &phy,  in elink_8726_common_init_phy()
14458 	struct elink_phy phy[PORT_MAX];  in elink_8727_common_init_phy()  local
14502 				       port_of_path, &phy[port]) !=  in elink_8727_common_init_phy()
14517 		elink_cl45_write(sc, &phy[port],  in elink_8727_common_init_phy()
14523 	if (phy[PORT_0].addr & 0x1) {  in elink_8727_common_init_phy()
14524 		phy_blk[PORT_0] = &(phy[PORT_1]);  in elink_8727_common_init_phy()
14525 		phy_blk[PORT_1] = &(phy[PORT_0]);  in elink_8727_common_init_phy()
14527 		phy_blk[PORT_0] = &(phy[PORT_0]);  in elink_8727_common_init_phy()
14528 		phy_blk[PORT_1] = &(phy[PORT_1]);  in elink_8727_common_init_phy()
14836 static void elink_sfp_tx_fault_detection(struct elink_phy *phy,  in elink_sfp_tx_fault_detection()  argument
14872 		if (!(phy->flags & ELINK_FLAGS_SFP_NOT_APPROVED)) {  in elink_sfp_tx_fault_detection()
14881 			       struct elink_phy *phy)  in elink_kr2_recovery()  argument
14885 	elink_warpcore_enable_AN_KR2(phy, params, vars);  in elink_kr2_recovery()
14886 	elink_warpcore_restart_AN_KR(phy, params);  in elink_kr2_recovery()
14891 			       struct elink_phy *phy)  in elink_check_kr2_wa()  argument
14907 	sigdet = elink_warpcore_get_sigdet(phy, params);  in elink_check_kr2_wa()
14910 			elink_kr2_recovery(params, vars, phy);  in elink_check_kr2_wa()
14916 	lane = elink_get_warpcore_lane(phy, params);  in elink_check_kr2_wa()
14917 	CL22_WR_OVER_CL45(sc, phy, MDIO_REG_BANK_AER_BLOCK,  in elink_check_kr2_wa()
14919 	elink_cl45_read(sc, phy, MDIO_AN_DEVAD,  in elink_check_kr2_wa()
14921 	elink_cl45_read(sc, phy, MDIO_AN_DEVAD,  in elink_check_kr2_wa()
14923 	elink_set_aer_mmd(params, phy);  in elink_check_kr2_wa()
14928 			elink_kr2_recovery(params, vars, phy);  in elink_check_kr2_wa()
14947 			elink_kr2_recovery(params, vars, phy);  in elink_check_kr2_wa()
14955 		elink_disable_kr2(params, vars, phy);  in elink_check_kr2_wa()
14957 		elink_warpcore_restart_AN_KR(phy, params);  in elink_check_kr2_wa()
14967 		if (params->phy[phy_idx].flags & ELINK_FLAGS_TX_ERROR_CHECK) {  in elink_period_func()
14968 			elink_set_aer_mmd(params, &params->phy[phy_idx]);  in elink_period_func()
14977 		struct elink_phy *phy = &params->phy[ELINK_INT_PHY];  in elink_period_func()  local
14978 		elink_set_aer_mmd(params, phy);  in elink_period_func()
14979 		if (((phy->req_line_speed == ELINK_SPEED_AUTO_NEG) &&  in elink_period_func()
14980 		     (phy->speed_cap_mask &  in elink_period_func()
14982 		    (phy->req_line_speed == ELINK_SPEED_20000))  in elink_period_func()
14983 			elink_check_kr2_wa(params, vars, phy);  in elink_period_func()
14986 			elink_warpcore_config_runtime(phy, params, vars);  in elink_period_func()
14993 			if (elink_is_sfp_module_plugged(phy, params)) {  in elink_period_func()
14994 				elink_sfp_tx_fault_detection(phy, params, vars);  in elink_period_func()
15013 	struct elink_phy phy;  in elink_fan_failure_det_req()  local
15017 				       port, &phy)  in elink_fan_failure_det_req()
15022 		fan_failure_det_req |= (phy.flags &  in elink_fan_failure_det_req()
15041 		if (params->phy[phy_index].hw_reset) {  in elink_hw_reset_phy()
15042 			params->phy[phy_index].hw_reset(  in elink_hw_reset_phy()
15043 				&params->phy[phy_index],  in elink_hw_reset_phy()
15045 			params->phy[phy_index] = phy_null;  in elink_hw_reset_phy()
15065 		struct elink_phy phy;  in elink_init_mod_abs_int()  local
15069 					       shmem2_base, port, &phy)  in elink_init_mod_abs_int()
15074 			if (phy.type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726) {  in elink_init_mod_abs_int()