Lines Matching refs:REG_WR
956 REG_WR(sc, reg, val); in elink_bits_en()
965 REG_WR(sc, reg, val); in elink_bits_dis()
993 REG_WR(sc, params->lfa_base + in elink_check_lfa()
1112 REG_WR(sc, MCP_REG_MCPR_GP_OENABLE, gp_oenable & ~epio_mask); in elink_get_epio()
1134 REG_WR(sc, MCP_REG_MCPR_GP_OUTPUTS, gp_output); in elink_set_epio()
1138 REG_WR(sc, MCP_REG_MCPR_GP_OENABLE, gp_oenable | epio_mask); in elink_set_epio()
1185 REG_WR(sc, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT, 0x4688); in elink_ets_e2e3a0_disabled()
1194 REG_WR(sc, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x7); in elink_ets_e2e3a0_disabled()
1196 REG_WR(sc, NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ, 0); in elink_ets_e2e3a0_disabled()
1200 REG_WR(sc, NIG_REG_P0_TX_ARB_NUM_STRICT_ARB_SLOTS, 0x100); in elink_ets_e2e3a0_disabled()
1204 REG_WR(sc, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP, 0); in elink_ets_e2e3a0_disabled()
1205 REG_WR(sc, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0, 0); in elink_ets_e2e3a0_disabled()
1206 REG_WR(sc, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1, 0); in elink_ets_e2e3a0_disabled()
1208 REG_WR(sc, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_0, 0); in elink_ets_e2e3a0_disabled()
1209 REG_WR(sc, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_1, 0); in elink_ets_e2e3a0_disabled()
1210 REG_WR(sc, PBF_REG_HIGH_PRIORITY_COS_NUM, 0); in elink_ets_e2e3a0_disabled()
1212 REG_WR(sc, PBF_REG_ETS_ENABLED, 0); in elink_ets_e2e3a0_disabled()
1216 REG_WR(sc, PBF_REG_COS0_WEIGHT, 0x2710); in elink_ets_e2e3a0_disabled()
1217 REG_WR(sc, PBF_REG_COS1_WEIGHT, 0x2710); in elink_ets_e2e3a0_disabled()
1219 REG_WR(sc, PBF_REG_COS0_UPPER_BOUND, 0x989680); in elink_ets_e2e3a0_disabled()
1220 REG_WR(sc, PBF_REG_COS1_UPPER_BOUND, 0x989680); in elink_ets_e2e3a0_disabled()
1222 REG_WR(sc, PBF_REG_NUM_STRICT_ARB_SLOTS, 0); in elink_ets_e2e3a0_disabled()
1270 REG_WR(sc, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_0 : in elink_ets_e3b0_set_credit_upper_bound_nig()
1272 REG_WR(sc, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_1 : in elink_ets_e3b0_set_credit_upper_bound_nig()
1274 REG_WR(sc, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_2 : in elink_ets_e3b0_set_credit_upper_bound_nig()
1276 REG_WR(sc, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_3 : in elink_ets_e3b0_set_credit_upper_bound_nig()
1278 REG_WR(sc, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_4 : in elink_ets_e3b0_set_credit_upper_bound_nig()
1280 REG_WR(sc, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_5 : in elink_ets_e3b0_set_credit_upper_bound_nig()
1284 REG_WR(sc, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_6, in elink_ets_e3b0_set_credit_upper_bound_nig()
1286 REG_WR(sc, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_7, in elink_ets_e3b0_set_credit_upper_bound_nig()
1288 REG_WR(sc, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_8, in elink_ets_e3b0_set_credit_upper_bound_nig()
1312 REG_WR(sc, NIG_REG_P1_TX_ARB_PRIORITY_CLIENT2_LSB, 0x543210); in elink_ets_e3b0_nig_disabled()
1313 REG_WR(sc, NIG_REG_P1_TX_ARB_PRIORITY_CLIENT2_MSB, 0x0); in elink_ets_e3b0_nig_disabled()
1315 REG_WR(sc, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_LSB, 0x76543210); in elink_ets_e3b0_nig_disabled()
1316 REG_WR(sc, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_MSB, 0x8); in elink_ets_e3b0_nig_disabled()
1321 REG_WR(sc, (port) ? NIG_REG_P1_TX_ARB_NUM_STRICT_ARB_SLOTS : in elink_ets_e3b0_nig_disabled()
1328 REG_WR(sc, NIG_REG_P1_TX_ARB_CLIENT_CREDIT_MAP2_LSB, 0x210543); in elink_ets_e3b0_nig_disabled()
1329 REG_WR(sc, NIG_REG_P1_TX_ARB_CLIENT_CREDIT_MAP2_MSB, 0x0); in elink_ets_e3b0_nig_disabled()
1332 REG_WR(sc, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP2_LSB, in elink_ets_e3b0_nig_disabled()
1334 REG_WR(sc, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP2_MSB, 0x5); in elink_ets_e3b0_nig_disabled()
1345 REG_WR(sc, NIG_REG_P1_TX_ARB_CLIENT_IS_STRICT, 0x3f); in elink_ets_e3b0_nig_disabled()
1347 REG_WR(sc, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x1ff); in elink_ets_e3b0_nig_disabled()
1349 REG_WR(sc, (port) ? NIG_REG_P1_TX_ARB_CLIENT_IS_SUBJECT2WFQ : in elink_ets_e3b0_nig_disabled()
1358 REG_WR(sc, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_0 : in elink_ets_e3b0_nig_disabled()
1360 REG_WR(sc, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_1 : in elink_ets_e3b0_nig_disabled()
1362 REG_WR(sc, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_2 : in elink_ets_e3b0_nig_disabled()
1364 REG_WR(sc, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_3 : in elink_ets_e3b0_nig_disabled()
1366 REG_WR(sc, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_4 : in elink_ets_e3b0_nig_disabled()
1368 REG_WR(sc, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_5 : in elink_ets_e3b0_nig_disabled()
1371 REG_WR(sc, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_6, 0x0); in elink_ets_e3b0_nig_disabled()
1372 REG_WR(sc, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_7, 0x0); in elink_ets_e3b0_nig_disabled()
1373 REG_WR(sc, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_8, 0x0); in elink_ets_e3b0_nig_disabled()
1406 REG_WR(sc, base_upper_bound + (i << 2), credit_upper_bound); in elink_ets_e3b0_set_credit_upper_bound_pbf()
1432 REG_WR(sc, PBF_REG_ETS_ARB_PRIORITY_CLIENT_P1 , 0x688); in elink_ets_e3b0_pbf_disabled()
1435 REG_WR(sc, PBF_REG_ETS_ARB_PRIORITY_CLIENT_P0 , 0x2C688); in elink_ets_e3b0_pbf_disabled()
1440 REG_WR(sc, PBF_REG_ETS_ARB_CLIENT_CREDIT_MAP_P1, 0x688); in elink_ets_e3b0_pbf_disabled()
1443 REG_WR(sc, PBF_REG_ETS_ARB_CLIENT_CREDIT_MAP_P0, 0x2C688); in elink_ets_e3b0_pbf_disabled()
1445 REG_WR(sc, (port) ? PBF_REG_ETS_ARB_NUM_STRICT_ARB_SLOTS_P1 : in elink_ets_e3b0_pbf_disabled()
1449 REG_WR(sc, (port) ? PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P1 : in elink_ets_e3b0_pbf_disabled()
1452 REG_WR(sc, (port) ? PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P1 : in elink_ets_e3b0_pbf_disabled()
1466 REG_WR(sc, base_weight + (0x4 * i), 0); in elink_ets_e3b0_pbf_disabled()
1533 REG_WR(sc, (port) ? NIG_REG_P1_TX_ARB_CLIENT_IS_STRICT : in elink_ets_e3b0_cli_map()
1536 REG_WR(sc, (port) ? PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P1 : in elink_ets_e3b0_cli_map()
1539 REG_WR(sc, (port) ? NIG_REG_P1_TX_ARB_CLIENT_IS_SUBJECT2WFQ : in elink_ets_e3b0_cli_map()
1543 REG_WR(sc, (port) ? PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P1 : in elink_ets_e3b0_cli_map()
1616 REG_WR(sc, nig_reg_adress_crd_weight, cos_bw_nig); in elink_ets_e3b0_set_cos_bw()
1618 REG_WR(sc, pbf_reg_adress_crd_weight, cos_bw_pbf); in elink_ets_e3b0_set_cos_bw()
1840 REG_WR(sc, NIG_REG_P1_TX_ARB_PRIORITY_CLIENT2_LSB, in elink_ets_e3b0_sp_set_pri_cli_reg()
1843 REG_WR(sc, PBF_REG_ETS_ARB_PRIORITY_CLIENT_P1 , pri_cli_pbf); in elink_ets_e3b0_sp_set_pri_cli_reg()
1849 REG_WR(sc, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_LSB, in elink_ets_e3b0_sp_set_pri_cli_reg()
1851 REG_WR(sc, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_MSB, in elink_ets_e3b0_sp_set_pri_cli_reg()
1854 REG_WR(sc, PBF_REG_ETS_ARB_PRIORITY_CLIENT_P0 , pri_cli_pbf); in elink_ets_e3b0_sp_set_pri_cli_reg()
1974 REG_WR(sc, NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ, 0x18); in elink_ets_bw_limit_common()
1981 REG_WR(sc, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP, 0x111A); in elink_ets_bw_limit_common()
1983 REG_WR(sc, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_0, in elink_ets_bw_limit_common()
1985 REG_WR(sc, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_1, in elink_ets_bw_limit_common()
1989 REG_WR(sc, PBF_REG_ETS_ENABLED, 1); in elink_ets_bw_limit_common()
1992 REG_WR(sc, PBF_REG_NUM_STRICT_ARB_SLOTS, 0); in elink_ets_bw_limit_common()
2000 REG_WR(sc, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x7); in elink_ets_bw_limit_common()
2003 REG_WR(sc, PBF_REG_COS0_UPPER_BOUND, in elink_ets_bw_limit_common()
2005 REG_WR(sc, PBF_REG_COS1_UPPER_BOUND, in elink_ets_bw_limit_common()
2034 REG_WR(sc, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0, cos0_credit_weight); in elink_ets_bw_limit()
2035 REG_WR(sc, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1, cos1_credit_weight); in elink_ets_bw_limit()
2037 REG_WR(sc, PBF_REG_COS0_WEIGHT, cos0_credit_weight); in elink_ets_bw_limit()
2038 REG_WR(sc, PBF_REG_COS1_WEIGHT, cos1_credit_weight); in elink_ets_bw_limit()
2055 REG_WR(sc, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x1F); in elink_ets_strict()
2059 REG_WR(sc, NIG_REG_P0_TX_ARB_NUM_STRICT_ARB_SLOTS, 0x100); in elink_ets_strict()
2061 REG_WR(sc, PBF_REG_ETS_ENABLED, 0); in elink_ets_strict()
2063 REG_WR(sc, PBF_REG_NUM_STRICT_ARB_SLOTS, 0x100); in elink_ets_strict()
2066 REG_WR(sc, PBF_REG_HIGH_PRIORITY_COS_NUM, strict_cos); in elink_ets_strict()
2076 REG_WR(sc, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT, val); in elink_ets_strict()
2119 REG_WR(sc, xmac_base + XMAC_REG_PAUSE_CTRL, pause_val); in elink_update_pfc_xmac()
2120 REG_WR(sc, xmac_base + XMAC_REG_PFC_CTRL, pfc0_val); in elink_update_pfc_xmac()
2121 REG_WR(sc, xmac_base + XMAC_REG_PFC_CTRL_HI, pfc1_val); in elink_update_pfc_xmac()
2127 REG_WR(sc, xmac_base + XMAC_REG_PAUSE_CTRL, pause_val); in elink_update_pfc_xmac()
2128 REG_WR(sc, xmac_base + XMAC_REG_PFC_CTRL, pfc0_val); in elink_update_pfc_xmac()
2129 REG_WR(sc, xmac_base + XMAC_REG_PFC_CTRL_HI, pfc1_val); in elink_update_pfc_xmac()
2133 REG_WR(sc, xmac_base + XMAC_REG_CTRL_SA_LO, in elink_update_pfc_xmac()
2138 REG_WR(sc, xmac_base + XMAC_REG_CTRL_SA_HI, in elink_update_pfc_xmac()
2224 REG_WR(sc, emac_base + EMAC_REG_EMAC_MDIO_MODE, new_mode); in elink_set_mdio_clk()
2263 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, in elink_emac_init()
2266 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, in elink_emac_init()
2304 REG_WR(sc, params->port ? NIG_REG_P1_MAC_IN_EN : NIG_REG_P0_MAC_IN_EN, in elink_set_xumac_nig()
2306 REG_WR(sc, params->port ? NIG_REG_P1_MAC_OUT_EN : NIG_REG_P0_MAC_OUT_EN, in elink_set_xumac_nig()
2308 REG_WR(sc, params->port ? NIG_REG_P1_MAC_PAUSE_OUT_EN : in elink_set_xumac_nig()
2328 REG_WR(sc, umac_base + UMAC_REG_COMMAND_CONFIG, val); in elink_set_umac_rxtx()
2338 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, in elink_umac_enable()
2342 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, in elink_umac_enable()
2348 REG_WR(sc, NIG_REG_EGRESS_EMAC0_PORT + params->port*4, 1); in elink_umac_enable()
2381 REG_WR(sc, umac_base + UMAC_REG_COMMAND_CONFIG, val); in elink_umac_enable()
2387 REG_WR(sc, umac_base + UMAC_REG_UMAC_EEE_CTRL, in elink_umac_enable()
2389 REG_WR(sc, umac_base + UMAC_REG_EEE_WAKE_TIMER, 0x11); in elink_umac_enable()
2391 REG_WR(sc, umac_base + UMAC_REG_UMAC_EEE_CTRL, 0x0); in elink_umac_enable()
2395 REG_WR(sc, umac_base + UMAC_REG_MAC_ADDR0, in elink_umac_enable()
2400 REG_WR(sc, umac_base + UMAC_REG_MAC_ADDR1, in elink_umac_enable()
2408 REG_WR(sc, umac_base + UMAC_REG_COMMAND_CONFIG, val); in elink_umac_enable()
2417 REG_WR(sc, umac_base + UMAC_REG_COMMAND_CONFIG, val); in elink_umac_enable()
2422 REG_WR(sc, umac_base + UMAC_REG_MAXFR, 0x2710); in elink_umac_enable()
2453 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, in elink_xmac_init()
2457 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, in elink_xmac_init()
2463 REG_WR(sc, MISC_REG_XMAC_CORE_PORT_MODE, 1); in elink_xmac_init()
2466 REG_WR(sc, MISC_REG_XMAC_PHY_PORT_MODE, 3); in elink_xmac_init()
2469 REG_WR(sc, MISC_REG_XMAC_CORE_PORT_MODE, 0); in elink_xmac_init()
2474 REG_WR(sc, MISC_REG_XMAC_PHY_PORT_MODE, 3); in elink_xmac_init()
2479 REG_WR(sc, MISC_REG_XMAC_PHY_PORT_MODE, 1); in elink_xmac_init()
2483 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, in elink_xmac_init()
2487 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, in elink_xmac_init()
2506 REG_WR(sc, xmac_base + XMAC_REG_PFC_CTRL_HI, in elink_set_xmac_rxtx()
2508 REG_WR(sc, xmac_base + XMAC_REG_PFC_CTRL_HI, in elink_set_xmac_rxtx()
2516 REG_WR(sc, xmac_base + XMAC_REG_CTRL, val); in elink_set_xmac_rxtx()
2538 REG_WR(sc, NIG_REG_EGRESS_EMAC0_PORT + params->port*4, 0); in elink_xmac_enable()
2544 REG_WR(sc, xmac_base + XMAC_REG_RX_LSS_CTRL, in elink_xmac_enable()
2547 REG_WR(sc, xmac_base + XMAC_REG_CLEAR_RX_LSS_STATUS, 0); in elink_xmac_enable()
2548 REG_WR(sc, xmac_base + XMAC_REG_CLEAR_RX_LSS_STATUS, in elink_xmac_enable()
2553 REG_WR(sc, xmac_base + XMAC_REG_RX_MAX_SIZE, 0x2710); in elink_xmac_enable()
2556 REG_WR(sc, xmac_base + XMAC_REG_TX_CTRL, 0xC800); in elink_xmac_enable()
2563 REG_WR(sc, xmac_base + XMAC_REG_EEE_TIMERS_HI, 0x1380008); in elink_xmac_enable()
2564 REG_WR(sc, xmac_base + XMAC_REG_EEE_CTRL, 0x1); in elink_xmac_enable()
2566 REG_WR(sc, xmac_base + XMAC_REG_EEE_CTRL, 0x0); in elink_xmac_enable()
2581 REG_WR(sc, xmac_base + XMAC_REG_CTRL, val); in elink_xmac_enable()
2601 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, in elink_emac_enable()
2605 REG_WR(sc, NIG_REG_EGRESS_EMAC0_PORT + port*4, 1); in elink_emac_enable()
2611 REG_WR(sc, NIG_REG_XGXS_LANE_SEL_P0 + port*4, 1); in elink_emac_enable()
2612 REG_WR(sc, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 1); in elink_emac_enable()
2622 REG_WR(sc, NIG_REG_XGXS_LANE_SEL_P0 + port*4, 1); in elink_emac_enable()
2623 REG_WR(sc, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 0); in elink_emac_enable()
2634 REG_WR(sc, NIG_REG_XGXS_LANE_SEL_P0 + port*4, ser_lane); in elink_emac_enable()
2636 REG_WR(sc, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 1); in elink_emac_enable()
2641 REG_WR(sc, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 0); in elink_emac_enable()
2720 REG_WR(sc, NIG_REG_NIG_EMAC0_EN + port*4, 1); in elink_emac_enable()
2728 REG_WR(sc, NIG_REG_NIG_INGRESS_EMAC0_NO_CRC + port*4, 0x1); in elink_emac_enable()
2731 REG_WR(sc, NIG_REG_BMAC0_IN_EN + port*4, 0x0); in elink_emac_enable()
2732 REG_WR(sc, NIG_REG_BMAC0_PAUSE_OUT_EN + port*4, 0x0); in elink_emac_enable()
2733 REG_WR(sc, NIG_REG_BMAC0_OUT_EN + port*4, 0x0); in elink_emac_enable()
2736 REG_WR(sc, NIG_REG_EMAC0_IN_EN + port*4, 0x1); in elink_emac_enable()
2743 REG_WR(sc, NIG_REG_EMAC0_PAUSE_OUT_EN + port*4, val); in elink_emac_enable()
2744 REG_WR(sc, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0x1); in elink_emac_enable()
2749 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, in elink_emac_enable()
2753 REG_WR(sc, NIG_REG_BMAC0_REGS_OUT_EN + port*4, 0x1); in elink_emac_enable()
2756 REG_WR(sc, NIG_REG_BMAC0_REGS_OUT_EN + port*4, 0x0); in elink_emac_enable()
2920 REG_WR(sc, nig_reg_rx_priority_mask_add, priority_mask); in elink_pfc_nig_rx_priority_mask()
2928 REG_WR(sc, params->shmem_base + in elink_update_mng()
2982 REG_WR(sc, port ? NIG_REG_BRB1_PAUSE_IN_EN : in elink_update_pfc_nig()
2984 REG_WR(sc, port ? NIG_REG_LLFC_OUT_EN_1 : in elink_update_pfc_nig()
2986 REG_WR(sc, port ? NIG_REG_LLFC_ENABLE_1 : in elink_update_pfc_nig()
2988 REG_WR(sc, port ? NIG_REG_PAUSE_ENABLE_1 : in elink_update_pfc_nig()
2991 REG_WR(sc, port ? NIG_REG_PPP_ENABLE_1 : in elink_update_pfc_nig()
2994 REG_WR(sc, port ? NIG_REG_LLH1_XCM_MASK : in elink_update_pfc_nig()
2997 REG_WR(sc, port ? NIG_REG_LLFC_EGRESS_SRC_ENABLE_1 : in elink_update_pfc_nig()
3001 REG_WR(sc, port ? NIG_REG_XCM1_OUT_EN : in elink_update_pfc_nig()
3005 REG_WR(sc, port ? NIG_REG_P1_HWPFC_ENABLE : in elink_update_pfc_nig()
3016 REG_WR(sc, port ? NIG_REG_LLFC_HIGH_PRIORITY_CLASSES_1 : in elink_update_pfc_nig()
3020 REG_WR(sc, port ? NIG_REG_LLFC_LOW_PRIORITY_CLASSES_1 : in elink_update_pfc_nig()
3024 REG_WR(sc, port ? NIG_REG_P1_PKT_PRIORITY_TO_COS : in elink_update_pfc_nig()
3078 REG_WR(sc, NIG_REG_BMAC0_PAUSE_OUT_EN + params->port*4, val); in elink_update_pfc()
3231 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, in elink_bmac_enable()
3236 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, in elink_bmac_enable()
3240 REG_WR(sc, NIG_REG_BMAC0_REGS_OUT_EN + port*4, 0x1); in elink_bmac_enable()
3247 REG_WR(sc, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 0x1); in elink_bmac_enable()
3248 REG_WR(sc, NIG_REG_XGXS_LANE_SEL_P0 + port*4, 0x0); in elink_bmac_enable()
3249 REG_WR(sc, NIG_REG_EGRESS_EMAC0_PORT + port*4, 0x0); in elink_bmac_enable()
3255 REG_WR(sc, NIG_REG_BMAC0_PAUSE_OUT_EN + port*4, val); in elink_bmac_enable()
3256 REG_WR(sc, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0x0); in elink_bmac_enable()
3257 REG_WR(sc, NIG_REG_EMAC0_IN_EN + port*4, 0x0); in elink_bmac_enable()
3258 REG_WR(sc, NIG_REG_EMAC0_PAUSE_OUT_EN + port*4, 0x0); in elink_bmac_enable()
3259 REG_WR(sc, NIG_REG_BMAC0_IN_EN + port*4, 0x1); in elink_bmac_enable()
3260 REG_WR(sc, NIG_REG_BMAC0_OUT_EN + port*4, 0x1); in elink_bmac_enable()
3301 REG_WR(sc, PBF_REG_DISABLE_NEW_TASK_PROC_P0 + port*4, 0x1); in elink_pbf_update()
3325 REG_WR(sc, PBF_REG_P0_PAUSE_ENABLE + port*4, 1); in elink_pbf_update()
3327 REG_WR(sc, PBF_REG_P0_ARB_THRSH + port*4, 0); in elink_pbf_update()
3334 REG_WR(sc, PBF_REG_P0_PAUSE_ENABLE + port*4, 0); in elink_pbf_update()
3336 REG_WR(sc, PBF_REG_P0_ARB_THRSH + port*4, thresh); in elink_pbf_update()
3348 REG_WR(sc, PBF_REG_P0_INIT_CRD + port*4, init_crd); in elink_pbf_update()
3353 REG_WR(sc, PBF_REG_INIT_P0 + port*4, 0x1); in elink_pbf_update()
3355 REG_WR(sc, PBF_REG_INIT_P0 + port*4, 0x0); in elink_pbf_update()
3358 REG_WR(sc, PBF_REG_DISABLE_NEW_TASK_PROC_P0 + port*4, 0x0); in elink_pbf_update()
3421 REG_WR(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, in elink_cl22_write()
3428 REG_WR(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp); in elink_cl22_write()
3443 REG_WR(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, mode); in elink_cl22_write()
3457 REG_WR(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, in elink_cl22_read()
3464 REG_WR(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val); in elink_cl22_read()
3482 REG_WR(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, mode); in elink_cl22_read()
3509 REG_WR(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val); in elink_cl45_read()
3531 REG_WR(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val); in elink_cl45_read()
3587 REG_WR(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp); in elink_cl45_write()
3608 REG_WR(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp); in elink_cl45_write()
3736 REG_WR(sc, MISC_REG_CPMU_LP_IDLE_THR_P0 + (params->port << 2), in elink_eee_set_timers()
3786 REG_WR(sc, MISC_REG_CPMU_LP_FW_ENABLE_P0 + (params->port << 2), 0); in elink_eee_disable()
3803 REG_WR(sc, MISC_REG_CPMU_LP_MASK_EXT_P0 + (params->port << 2), 0xfc20); in elink_eee_advertise()
3827 REG_WR(sc, params->shmem2_base + in elink_update_mng_eee()
3928 REG_WR(sc, MCP_REG_MCPR_IMC_COMMAND, val); in elink_bsc_read()
3932 REG_WR(sc, MCP_REG_MCPR_IMC_SLAVE_CONTROL, val); in elink_bsc_read()
3939 REG_WR(sc, MCP_REG_MCPR_IMC_COMMAND, val); in elink_bsc_read()
3963 REG_WR(sc, MCP_REG_MCPR_IMC_COMMAND, val); in elink_bsc_read()
4140 REG_WR(sc, NIG_REG_SERDES0_CTRL_MD_ST + port*0x10, 1); in elink_set_serdes_access()
4141 REG_WR(sc, emac_base + EMAC_REG_EMAC_MDIO_COMM, 0x245f8000); in elink_set_serdes_access()
4143 REG_WR(sc, emac_base + EMAC_REG_EMAC_MDIO_COMM, 0x245d000f); in elink_set_serdes_access()
4146 REG_WR(sc, NIG_REG_SERDES0_CTRL_MD_ST + port*0x10, 0); in elink_set_serdes_access()
4158 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR, val); in elink_serdes_deassert()
4160 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_SET, val); in elink_serdes_deassert()
4164 REG_WR(sc, NIG_REG_SERDES0_CTRL_MD_DEVAD + port*0x10, in elink_serdes_deassert()
4176 REG_WR(sc, NIG_REG_XGXS0_CTRL_MD_ST + params->port*0x18, 0); in elink_xgxs_specific_func()
4177 REG_WR(sc, NIG_REG_XGXS0_CTRL_MD_DEVAD + params->port*0x18, in elink_xgxs_specific_func()
4194 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR, val); in elink_xgxs_deassert()
4196 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_SET, val); in elink_xgxs_deassert()
4456 REG_WR(sc, params->shmem2_base + in elink_update_link_attr()
6976 REG_WR(sc, NIG_REG_LATCH_STATUS_0 + port*8, in elink_rearm_latch_signal()
7124 REG_WR(sc, NIG_REG_XGXS0_CTRL_MD_DEVAD + port*0x18, in elink_set_xgxs_loopback()
7145 REG_WR(sc, NIG_REG_XGXS0_CTRL_MD_DEVAD + port*0x18, in elink_set_xgxs_loopback()
7192 REG_WR(sc, NIG_REG_LED_10G_P0 + port*4, 0); in elink_set_led()
7193 REG_WR(sc, NIG_REG_LED_MODE_P0 + port*4, in elink_set_led()
7223 REG_WR(sc, NIG_REG_LED_MODE_P0 + port*4, 0); in elink_set_led()
7224 REG_WR(sc, NIG_REG_LED_10G_P0 + port*4, 1); in elink_set_led()
7244 REG_WR(sc, NIG_REG_LED_10G_P0 + port*4, 1); in elink_set_led()
7249 REG_WR(sc, NIG_REG_LED_MODE_P0 + port*4, 0); in elink_set_led()
7251 REG_WR(sc, NIG_REG_LED_MODE_P0 + port*4, in elink_set_led()
7256 REG_WR(sc, NIG_REG_LED_MODE_P0 + port*4, 0); in elink_set_led()
7270 REG_WR(sc, NIG_REG_LED_MODE_P0 + port*4, in elink_set_led()
7274 REG_WR(sc, NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0 + port*4, 0); in elink_set_led()
7277 REG_WR(sc, NIG_REG_LED_CONTROL_BLINK_RATE_P0 + port*4, in elink_set_led()
7280 REG_WR(sc, NIG_REG_LED_CONTROL_BLINK_RATE_P0 + port*4, in elink_set_led()
7282 REG_WR(sc, NIG_REG_LED_CONTROL_BLINK_RATE_ENA_P0 + in elink_set_led()
7294 REG_WR(sc, NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0 in elink_set_led()
7296 REG_WR(sc, NIG_REG_LED_CONTROL_TRAFFIC_P0 + in elink_set_led()
7298 REG_WR(sc, NIG_REG_LED_CONTROL_BLINK_TRAFFIC_P0 + in elink_set_led()
7487 REG_WR(params->sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR, in elink_int_link_reset()
7528 REG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 1); in elink_update_link_down()
7532 REG_WR(sc, NIG_REG_NIG_EMAC0_EN + port*4, 0); in elink_update_link_down()
7542 REG_WR(sc, MISC_REG_CPMU_LP_FW_ENABLE_P0 + (params->port << 2), in elink_update_link_down()
7544 REG_WR(sc, MISC_REG_CPMU_LP_MASK_ENT_P0 + (params->port << 2), in elink_update_link_down()
7593 REG_WR(sc, MISC_REG_CPMU_LP_FW_ENABLE_P0 + in elink_update_link_up()
7595 REG_WR(sc, MISC_REG_CPMU_LP_DR_ENABLE, 1); in elink_update_link_up()
7596 REG_WR(sc, MISC_REG_CPMU_LP_MASK_ENT_P0 + in elink_update_link_up()
7632 REG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 0); in elink_update_link_up()
7663 REG_WR(sc, addr, val); in elink_chng_link_count()
7722 REG_WR(sc, NIG_REG_NIG_EMAC0_EN + port*4, 0); in elink_link_update()
7877 REG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, in elink_link_update()
7970 REG_WR(sc, ver_addr, spirom_ver); in elink_save_spirom_version()
9140 REG_WR(sc, sync_offset, media_types); in elink_get_edc_mode()
9501 REG_WR(sc, MISC_REG_WC0_RESET, 0x0c0e); in elink_warpcore_hw_reset()
9504 REG_WR(sc, MISC_REG_LCPLL_E40_PWRDWN, 1); in elink_warpcore_hw_reset()
9505 REG_WR(sc, MISC_REG_LCPLL_E40_RESETB_ANA, 0); in elink_warpcore_hw_reset()
9506 REG_WR(sc, MISC_REG_LCPLL_E40_RESETB_DIG, 0); in elink_warpcore_hw_reset()
12248 REG_WR(sc, NIG_REG_EGRESS_EMAC0_PORT + params->port*4, 1); in elink_54618se_config_loopback()
12253 REG_WR(sc, umac_base + UMAC_REG_MAXFR, 0x2710); in elink_54618se_config_loopback()
13475 REG_WR(sc, sync_offset, media_types); in elink_phy_probe()
13600 REG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0); in elink_init_emul()
13662 REG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0); in elink_init_fpga()
13686 REG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0); in elink_init_bmac_loopback()
13705 REG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0); in elink_init_emac_loopback()
13731 REG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0); in elink_init_xmac_loopback()
13746 REG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0); in elink_init_umac_loopback()
13796 REG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0); in elink_init_xgxs_loopback()
13809 REG_WR(sc, NIG_REG_LLH0_BRB1_DRV_MASK + params->port*4, val); in elink_set_rx_filter()
13812 REG_WR(sc, NIG_REG_LLH0_BRB1_DRV_MASK_MF + params->port*4, in elink_set_rx_filter()
13816 REG_WR(sc, (params->port ? NIG_REG_LLH1_BRB1_NOT_MCP : in elink_set_rx_filter()
13855 REG_WR(sc, GRCBASE_MISC + in elink_avoid_link_flap()
13859 REG_WR(sc, GRCBASE_MISC + in elink_avoid_link_flap()
13883 REG_WR(sc, params->lfa_base + in elink_avoid_link_flap()
13887 REG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0); in elink_avoid_link_flap()
13906 REG_WR(sc, params->lfa_base + in elink_cannot_avoid_link_flap()
13910 REG_WR(sc, params->lfa_base + in elink_cannot_avoid_link_flap()
13914 REG_WR(sc, params->lfa_base + in elink_cannot_avoid_link_flap()
13919 REG_WR(sc, params->lfa_base + in elink_cannot_avoid_link_flap()
13930 REG_WR(sc, params->lfa_base + in elink_cannot_avoid_link_flap()
13949 REG_WR(sc, params->lfa_base + in elink_cannot_avoid_link_flap()
14090 REG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 1); in elink_link_reset()
14094 REG_WR(sc, NIG_REG_BMAC0_OUT_EN + port*4, 0); in elink_link_reset()
14095 REG_WR(sc, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0); in elink_link_reset()
14117 REG_WR(sc, NIG_REG_NIG_EMAC0_EN + port*4, 0); in elink_link_reset()
14159 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, in elink_link_reset()
14161 REG_WR(sc, NIG_REG_BMAC0_IN_EN + port*4, 0); in elink_link_reset()
14162 REG_WR(sc, NIG_REG_EMAC0_IN_EN + port*4, 0); in elink_link_reset()
14168 REG_WR(sc, xmac_base + XMAC_REG_CTRL, in elink_link_reset()
14188 REG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 1); in elink_lfa_reset()
14223 REG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0); in elink_lfa_reset()
14369 REG_WR(sc, MISC_REG_GPIO_EVENT_EN, val); in elink_8726_common_init_phy()
14639 REG_WR(sc, MISC_REG_GEN_PURP_HWG, val | 1); in elink_common_init_phy()
14741 REG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 1); in elink_analyze_link_error()
14754 REG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0); in elink_analyze_link_error()
14804 REG_WR(sc, mac_base + XMAC_REG_CLEAR_RX_LSS_STATUS, 0); in elink_check_half_open_conn()
14805 REG_WR(sc, mac_base + XMAC_REG_CLEAR_RX_LSS_STATUS, in elink_check_half_open_conn()
15098 REG_WR(sc, sync_offset, vars->aeu_int_mask); in elink_init_mod_abs_int()
15111 REG_WR(sc, offset, aeu_mask); in elink_init_mod_abs_int()
15116 REG_WR(sc, MISC_REG_GPIO_EVENT_EN, val); in elink_init_mod_abs_int()