Lines Matching refs:MDIO_WC_DEVAD
580 #define MDIO_WC_DEVAD 0x3 macro
4469 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL5, 0xa157}, in elink_warpcore_enable_AN_KR2()
4470 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL7, 0xcbe2}, in elink_warpcore_enable_AN_KR2()
4471 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL6, 0x7537}, in elink_warpcore_enable_AN_KR2()
4472 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL9, 0xa157}, in elink_warpcore_enable_AN_KR2()
4473 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_RX_CTRL11, 0xcbe2}, in elink_warpcore_enable_AN_KR2()
4474 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_RX_CTRL10, 0x7537}, in elink_warpcore_enable_AN_KR2()
4476 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_USERB0_CTRL, 0x000a}, in elink_warpcore_enable_AN_KR2()
4477 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_BAM_CTRL1, 0x6400}, in elink_warpcore_enable_AN_KR2()
4478 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_BAM_CTRL3, 0x0620}, in elink_warpcore_enable_AN_KR2()
4479 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_BAM_CODE_FIELD, 0x0157}, in elink_warpcore_enable_AN_KR2()
4480 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_OUI1, 0x6464}, in elink_warpcore_enable_AN_KR2()
4481 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_OUI2, 0x3150}, in elink_warpcore_enable_AN_KR2()
4482 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_OUI3, 0x3150}, in elink_warpcore_enable_AN_KR2()
4483 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_LD_BAM_CODE, 0x0157}, in elink_warpcore_enable_AN_KR2()
4484 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_LD_UD_CODE, 0x0620} in elink_warpcore_enable_AN_KR2()
4488 elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD, in elink_warpcore_enable_AN_KR2()
4508 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL5, 0x7690}, in elink_disable_kr2()
4509 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL7, 0xe647}, in elink_disable_kr2()
4510 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL6, 0xc4f0}, in elink_disable_kr2()
4511 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL9, 0x7690}, in elink_disable_kr2()
4512 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_RX_CTRL11, 0xe647}, in elink_disable_kr2()
4513 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_RX_CTRL10, 0xc4f0}, in elink_disable_kr2()
4514 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_USERB0_CTRL, 0x000c}, in elink_disable_kr2()
4515 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_BAM_CTRL1, 0x6000}, in elink_disable_kr2()
4516 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_BAM_CTRL3, 0x0000}, in elink_disable_kr2()
4517 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_BAM_CODE_FIELD, 0x0002}, in elink_disable_kr2()
4518 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_OUI1, 0x0000}, in elink_disable_kr2()
4519 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_OUI2, 0x0af7}, in elink_disable_kr2()
4520 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_OUI3, 0x0af7}, in elink_disable_kr2()
4521 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_LD_BAM_CODE, 0x0002}, in elink_disable_kr2()
4522 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_LD_UD_CODE, 0x0000} in elink_disable_kr2()
4541 elink_cl45_write(sc, phy, MDIO_WC_DEVAD, in elink_warpcore_set_lpi_passthrough()
4543 elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD, in elink_warpcore_set_lpi_passthrough()
4569 {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, 0x7}, in elink_warpcore_enable_AN_KR()
4571 {MDIO_WC_DEVAD, MDIO_WC_REG_RX66_CONTROL, 0x7415}, in elink_warpcore_enable_AN_KR()
4572 {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_MISC2, 0x6190}, in elink_warpcore_enable_AN_KR()
4576 {MDIO_WC_DEVAD, MDIO_WC_REG_CL72_USERB0_CL72_TX_FIR_TAP, 0}, in elink_warpcore_enable_AN_KR()
4584 elink_cl45_read(sc, phy, MDIO_WC_DEVAD, in elink_warpcore_enable_AN_KR()
4588 elink_cl45_write(sc, phy, MDIO_WC_DEVAD, in elink_warpcore_enable_AN_KR()
4599 elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD, addr, 0x1); in elink_warpcore_enable_AN_KR()
4619 elink_cl45_write(sc, phy, MDIO_WC_DEVAD, in elink_warpcore_enable_AN_KR()
4624 elink_cl45_write(sc, phy, MDIO_WC_DEVAD, in elink_warpcore_enable_AN_KR()
4627 elink_cl45_write(sc, phy, MDIO_WC_DEVAD, in elink_warpcore_enable_AN_KR()
4630 elink_cl45_write(sc, phy, MDIO_WC_DEVAD, in elink_warpcore_enable_AN_KR()
4649 elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD, in elink_warpcore_enable_AN_KR()
4658 elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD, in elink_warpcore_enable_AN_KR()
4662 elink_cl45_write(sc, phy, MDIO_WC_DEVAD, in elink_warpcore_enable_AN_KR()
4672 elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD, in elink_warpcore_enable_AN_KR()
4676 elink_cl45_write(sc, phy, MDIO_WC_DEVAD, in elink_warpcore_enable_AN_KR()
4683 elink_cl45_write(sc, phy, MDIO_WC_DEVAD, in elink_warpcore_enable_AN_KR()
4688 elink_cl45_read(sc, phy, MDIO_WC_DEVAD, in elink_warpcore_enable_AN_KR()
4703 elink_cl45_write(sc, phy, MDIO_WC_DEVAD, in elink_warpcore_enable_AN_KR()
4722 {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, 0x7}, in elink_warpcore_set_10G_KR()
4723 {MDIO_WC_DEVAD, MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL, in elink_warpcore_set_10G_KR()
4727 {MDIO_WC_DEVAD, MDIO_WC_REG_DIGITAL3_UP1, 0x1}, in elink_warpcore_set_10G_KR()
4728 {MDIO_WC_DEVAD, MDIO_WC_REG_DIGITAL5_MISC7, 0xa}, in elink_warpcore_set_10G_KR()
4742 elink_cl45_read(sc, phy, MDIO_WC_DEVAD, in elink_warpcore_set_10G_KR()
4745 elink_cl45_write(sc, phy, MDIO_WC_DEVAD, in elink_warpcore_set_10G_KR()
4748 elink_cl45_read(sc, phy, MDIO_WC_DEVAD, in elink_warpcore_set_10G_KR()
4751 elink_cl45_write(sc, phy, MDIO_WC_DEVAD, in elink_warpcore_set_10G_KR()
4763 elink_cl45_write(sc, phy, MDIO_WC_DEVAD, in elink_warpcore_set_10G_KR()
4767 elink_cl45_write(sc, phy, MDIO_WC_DEVAD, in elink_warpcore_set_10G_KR()
4771 elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD, in elink_warpcore_set_10G_KR()
4775 elink_cl45_write(sc, phy, MDIO_WC_DEVAD, in elink_warpcore_set_10G_KR()
4777 elink_cl45_write(sc, phy, MDIO_WC_DEVAD, in elink_warpcore_set_10G_KR()
4791 elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD, in elink_warpcore_set_10G_XFI()
4795 elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD, in elink_warpcore_set_10G_XFI()
4802 elink_cl45_read_and_write(sc, phy, MDIO_WC_DEVAD, in elink_warpcore_set_10G_XFI()
4806 elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD, in elink_warpcore_set_10G_XFI()
4810 elink_cl45_read_and_write(sc, phy, MDIO_WC_DEVAD, in elink_warpcore_set_10G_XFI()
4814 elink_cl45_read_and_write(sc, phy, MDIO_WC_DEVAD, in elink_warpcore_set_10G_XFI()
4819 elink_cl45_read(sc, phy, MDIO_WC_DEVAD, in elink_warpcore_set_10G_XFI()
4821 elink_cl45_write(sc, phy, MDIO_WC_DEVAD, in elink_warpcore_set_10G_XFI()
4826 elink_cl45_read(sc, phy, MDIO_WC_DEVAD, in elink_warpcore_set_10G_XFI()
4882 elink_cl45_write(sc, phy, MDIO_WC_DEVAD, in elink_warpcore_set_10G_XFI()
4887 elink_cl45_write(sc, phy, MDIO_WC_DEVAD, in elink_warpcore_set_10G_XFI()
4890 elink_cl45_write(sc, phy, MDIO_WC_DEVAD, in elink_warpcore_set_10G_XFI()
4895 elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD, in elink_warpcore_set_10G_XFI()
4899 elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD, in elink_warpcore_set_10G_XFI()
4905 elink_cl45_write(sc, phy, MDIO_WC_DEVAD, in elink_warpcore_set_10G_XFI()
4909 elink_cl45_read_and_write(sc, phy, MDIO_WC_DEVAD, in elink_warpcore_set_10G_XFI()
4913 elink_cl45_read_and_write(sc, phy, MDIO_WC_DEVAD, in elink_warpcore_set_10G_XFI()
4927 elink_cl45_read_and_write(sc, phy, MDIO_WC_DEVAD, in elink_warpcore_set_20G_force_KR2()
4937 elink_cl45_read(sc, phy, MDIO_WC_DEVAD, in elink_warpcore_set_20G_force_KR2()
4941 elink_cl45_write(sc, phy, MDIO_WC_DEVAD, in elink_warpcore_set_20G_force_KR2()
4945 elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD, in elink_warpcore_set_20G_force_KR2()
4948 elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD, in elink_warpcore_set_20G_force_KR2()
4951 elink_cl45_read(sc, phy, MDIO_WC_DEVAD, in elink_warpcore_set_20G_force_KR2()
4955 elink_cl45_write(sc, phy, MDIO_WC_DEVAD, in elink_warpcore_set_20G_force_KR2()
4957 elink_cl45_write(sc, phy, MDIO_WC_DEVAD, in elink_warpcore_set_20G_force_KR2()
4964 elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD, in elink_warpcore_set_20G_force_KR2()
4975 elink_cl45_write(sc, phy, MDIO_WC_DEVAD, in elink_warpcore_set_20G_DXGXS()
4979 elink_cl45_write(sc, phy, MDIO_WC_DEVAD, in elink_warpcore_set_20G_DXGXS()
4982 elink_cl45_write(sc, phy, MDIO_WC_DEVAD, in elink_warpcore_set_20G_DXGXS()
4985 elink_cl45_write(sc, phy, MDIO_WC_DEVAD, in elink_warpcore_set_20G_DXGXS()
4988 elink_cl45_write(sc, phy, MDIO_WC_DEVAD, in elink_warpcore_set_20G_DXGXS()
4991 elink_cl45_write(sc, phy, MDIO_WC_DEVAD, in elink_warpcore_set_20G_DXGXS()
4994 elink_cl45_write(sc, phy, MDIO_WC_DEVAD, in elink_warpcore_set_20G_DXGXS()
4997 elink_cl45_write(sc, phy, MDIO_WC_DEVAD, in elink_warpcore_set_20G_DXGXS()
5000 elink_cl45_write(sc, phy, MDIO_WC_DEVAD, in elink_warpcore_set_20G_DXGXS()
5003 elink_cl45_write(sc, phy, MDIO_WC_DEVAD, in elink_warpcore_set_20G_DXGXS()
5007 elink_cl45_write(sc, phy, MDIO_WC_DEVAD, in elink_warpcore_set_20G_DXGXS()
5011 elink_cl45_write(sc, phy, MDIO_WC_DEVAD, in elink_warpcore_set_20G_DXGXS()
5015 elink_cl45_write(sc, phy, MDIO_WC_DEVAD, in elink_warpcore_set_20G_DXGXS()
5019 elink_cl45_write(sc, phy, MDIO_WC_DEVAD, in elink_warpcore_set_20G_DXGXS()
5033 elink_cl45_read_and_write(sc, phy, MDIO_WC_DEVAD, in elink_warpcore_set_sgmii_speed()
5040 elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD, in elink_warpcore_set_sgmii_speed()
5045 elink_cl45_read(sc, phy, MDIO_WC_DEVAD, in elink_warpcore_set_sgmii_speed()
5066 elink_cl45_write(sc, phy, MDIO_WC_DEVAD, in elink_warpcore_set_sgmii_speed()
5071 elink_cl45_read(sc, phy, MDIO_WC_DEVAD, in elink_warpcore_set_sgmii_speed()
5077 elink_cl45_read(sc, phy, MDIO_WC_DEVAD, in elink_warpcore_set_sgmii_speed()
5084 elink_cl45_write(sc, phy, MDIO_WC_DEVAD, in elink_warpcore_set_sgmii_speed()
5089 elink_cl45_read(sc, phy, MDIO_WC_DEVAD, in elink_warpcore_set_sgmii_speed()
5091 elink_cl45_write(sc, phy, MDIO_WC_DEVAD, in elink_warpcore_set_sgmii_speed()
5096 elink_cl45_write(sc, phy, MDIO_WC_DEVAD, in elink_warpcore_set_sgmii_speed()
5101 elink_cl45_write(sc, phy, MDIO_WC_DEVAD, in elink_warpcore_set_sgmii_speed()
5113 elink_cl45_read(sc, phy, MDIO_WC_DEVAD, in elink_warpcore_reset_lane()
5119 elink_cl45_write(sc, phy, MDIO_WC_DEVAD, in elink_warpcore_reset_lane()
5121 elink_cl45_read(sc, phy, MDIO_WC_DEVAD, in elink_warpcore_reset_lane()
5134 {MDIO_WC_DEVAD, MDIO_WC_REG_FX100_CTRL1, 0x014a}, in elink_warpcore_clear_regs()
5135 {MDIO_WC_DEVAD, MDIO_WC_REG_FX100_CTRL3, 0x0800}, in elink_warpcore_clear_regs()
5136 {MDIO_WC_DEVAD, MDIO_WC_REG_DIGITAL4_MISC3, 0x8008}, in elink_warpcore_clear_regs()
5137 {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, in elink_warpcore_clear_regs()
5139 {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, in elink_warpcore_clear_regs()
5141 {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3, in elink_warpcore_clear_regs()
5143 {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_MISC1, 0x6000}, in elink_warpcore_clear_regs()
5144 {MDIO_WC_DEVAD, MDIO_WC_REG_TX_FIR_TAP, 0x0000}, in elink_warpcore_clear_regs()
5145 {MDIO_WC_DEVAD, MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x2040}, in elink_warpcore_clear_regs()
5146 {MDIO_WC_DEVAD, MDIO_WC_REG_COMBO_IEEE0_MIICTRL, 0x0140} in elink_warpcore_clear_regs()
5149 elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD, in elink_warpcore_clear_regs()
5157 elink_cl45_write(sc, phy, MDIO_WC_DEVAD, in elink_warpcore_clear_regs()
5227 elink_cl45_read(sc, phy, MDIO_WC_DEVAD, MDIO_WC_REG_GP2_STATUS_GP_2_0, in elink_warpcore_get_sigdet()
5256 elink_cl45_read(sc, phy, MDIO_WC_DEVAD, 0x81d1, in elink_warpcore_config_runtime()
5445 elink_cl45_read_and_write(sc, phy, MDIO_WC_DEVAD, in elink_warpcore_link_reset()
5448 elink_cl45_read_and_write(sc, phy, MDIO_WC_DEVAD, in elink_warpcore_link_reset()
5455 elink_cl45_read_and_write(sc, phy, MDIO_WC_DEVAD, in elink_warpcore_link_reset()
5459 elink_cl45_read_and_write(sc, phy, MDIO_WC_DEVAD, in elink_warpcore_link_reset()
5463 elink_cl45_read(sc, phy, MDIO_WC_DEVAD, in elink_warpcore_link_reset()
5468 elink_cl45_write(sc, phy, MDIO_WC_DEVAD, in elink_warpcore_link_reset()
5471 elink_cl45_read(sc, phy, MDIO_WC_DEVAD, in elink_warpcore_link_reset()
5480 elink_cl45_write(sc, phy, MDIO_WC_DEVAD, in elink_warpcore_link_reset()
5504 elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD, in elink_set_warpcore_loopback()
5509 elink_cl45_read(sc, phy, MDIO_WC_DEVAD, in elink_set_warpcore_loopback()
5514 elink_cl45_write(sc, phy, MDIO_WC_DEVAD, in elink_set_warpcore_loopback()
5522 elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD, in elink_set_warpcore_loopback()
5525 elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD, in elink_set_warpcore_loopback()
6549 elink_cl45_read(sc, phy, MDIO_WC_DEVAD, in elink_warpcore_read_status()
6551 elink_cl45_read(sc, phy, MDIO_WC_DEVAD, in elink_warpcore_read_status()
6559 elink_cl45_read(sc, phy, MDIO_WC_DEVAD, in elink_warpcore_read_status()
6561 elink_cl45_read(sc, phy, MDIO_WC_DEVAD, in elink_warpcore_read_status()
6569 elink_cl45_read(sc, phy, MDIO_WC_DEVAD, in elink_warpcore_read_status()
6592 elink_cl45_read(sc, phy, MDIO_WC_DEVAD, in elink_warpcore_read_status()
6600 elink_cl45_read(sc, phy, MDIO_WC_DEVAD, in elink_warpcore_read_status()
6633 elink_cl45_read(sc, phy, MDIO_WC_DEVAD, in elink_warpcore_read_status()
6649 elink_cl45_read(sc, phy, MDIO_WC_DEVAD, in elink_warpcore_read_status()
6652 elink_cl45_read(sc, phy, MDIO_WC_DEVAD, in elink_warpcore_read_status()
7338 elink_cl45_read(sc, int_phy, MDIO_WC_DEVAD, in elink_test_link()
7340 elink_cl45_read(sc, int_phy, MDIO_WC_DEVAD, in elink_test_link()
7346 elink_cl45_read(sc, int_phy, MDIO_WC_DEVAD, in elink_test_link()
9538 elink_cl45_read(sc, phy, MDIO_WC_DEVAD, in elink_warpcore_set_limiting_mode()
9556 elink_cl45_write(sc, phy, MDIO_WC_DEVAD, in elink_warpcore_set_limiting_mode()
9559 elink_cl45_read(sc, phy, MDIO_WC_DEVAD, in elink_warpcore_set_limiting_mode()
9685 MDIO_WC_DEVAD, in elink_handle_module_detect_int()
11804 elink_cl45_read(sc, phy, MDIO_WC_DEVAD, in elink_848xx_set_link_led()