Lines Matching refs:REG_WR
1036 REG_WR(sc, (hw_lock_control_reg + 4), resource_bit); in bxe_acquire_hw_lock()
1080 REG_WR(sc, hw_lock_control_reg, resource_bit); in bxe_release_hw_lock()
1125 REG_WR(sc, MCP_REG_MCPR_NVM_SW_ARB, in bxe_acquire_nvram_lock()
1161 REG_WR(sc, MCP_REG_MCPR_NVM_SW_ARB, in bxe_release_nvram_lock()
1194 REG_WR(sc, MCP_REG_MCPR_NVM_ACCESS_ENABLE, in bxe_enable_nvram_access()
1206 REG_WR(sc, MCP_REG_MCPR_NVM_ACCESS_ENABLE, in bxe_disable_nvram_access()
1224 REG_WR(sc, MCP_REG_MCPR_NVM_COMMAND, MCPR_NVM_COMMAND_DONE); in bxe_nvram_read_dword()
1227 REG_WR(sc, MCP_REG_MCPR_NVM_ADDR, in bxe_nvram_read_dword()
1231 REG_WR(sc, MCP_REG_MCPR_NVM_COMMAND, cmd_flags); in bxe_nvram_read_dword()
1337 REG_WR(sc, MCP_REG_MCPR_NVM_COMMAND, MCPR_NVM_COMMAND_DONE); in bxe_nvram_write_dword()
1340 REG_WR(sc, MCP_REG_MCPR_NVM_WRITE, val); in bxe_nvram_write_dword()
1343 REG_WR(sc, MCP_REG_MCPR_NVM_ADDR, in bxe_nvram_write_dword()
1347 REG_WR(sc, MCP_REG_MCPR_NVM_COMMAND, cmd_flags); in bxe_nvram_write_dword()
1508 REG_WR(sc, (cmd_offset + (i * 4)), *(((uint32_t *)dmae) + i)); in bxe_post_dmae()
1511 REG_WR(sc, dmae_reg_go_c[idx], 1); in bxe_post_dmae()
1817 REG_WR(sc, reg_addr, val); in elink_cb_reg_write()
1896 REG_WR(sc, MISC_REG_SPIO, spio_reg); in bxe_set_spio()
1986 REG_WR(sc, MISC_REG_GPIO, gpio_reg); in bxe_gpio_write()
2035 REG_WR(sc, MISC_REG_GPIO, gpio_reg); in bxe_gpio_mult_write()
2090 REG_WR(sc, MISC_REG_GPIO_INT, gpio_reg); in bxe_gpio_int_write()
2133 REG_WR(sc, (MISC_REG_AEU_GENERAL_ATTN_12 + in elink_cb_notify_link_changed()
2196 REG_WR(sc, addr, U64_LO(mapping)); in __storm_memset_dma_mapping()
2197 REG_WR(sc, (addr + 4), U64_HI(mapping)); in __storm_memset_dma_mapping()
4039 REG_WR(sc, NIG_REG_LLH0_FUNC_EN + port*8, 0); in bxe_chip_cleanup()
4138 REG_WR(sc, addr, val); in bxe_disable_close_the_gate()
4143 REG_WR(sc, MISC_REG_AEU_GENERAL_MASK, val); in bxe_disable_close_the_gate()
6608 REG_WR(sc, BXE_RECOVERY_GLOB_REG, val | BXE_GLOBAL_RESET_BIT); in bxe_set_reset_global()
6619 REG_WR(sc, BXE_RECOVERY_GLOB_REG, val & (~BXE_GLOBAL_RESET_BIT)); in bxe_clear_reset_global()
6645 REG_WR(sc, BXE_RECOVERY_GLOB_REG, val); in bxe_set_reset_done()
6663 REG_WR(sc, BXE_RECOVERY_GLOB_REG, val); in bxe_set_reset_in_progress()
6730 REG_WR(sc, BXE_RECOVERY_GLOB_REG, val); in bxe_set_pf_load()
6762 REG_WR(sc, BXE_RECOVERY_GLOB_REG, val); in bxe_clear_pf_load()
6869 REG_WR(sc, in bxe_nic_load_pmf()
6922 REG_WR(sc, GRCBASE_MCP + 0x9c, val); in bxe_acquire_alr()
6941 REG_WR(sc, GRCBASE_MCP + 0x9c, 0); in bxe_release_alr()
7003 REG_WR(sc, in bxe_link_attn()
7075 REG_WR(sc, aeu_addr, aeu_mask); in bxe_attn_int_asserted()
7092 REG_WR(sc, nig_int_mask_addr, 0); in bxe_attn_int_asserted()
7119 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_1, 0x0); in bxe_attn_int_asserted()
7123 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_2, 0x0); in bxe_attn_int_asserted()
7127 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_3, 0x0); in bxe_attn_int_asserted()
7132 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_4, 0x0); in bxe_attn_int_asserted()
7136 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_5, 0x0); in bxe_attn_int_asserted()
7140 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_6, 0x0); in bxe_attn_int_asserted()
7154 REG_WR(sc, reg_addr, asserted); in bxe_attn_int_asserted()
7177 REG_WR(sc, nig_int_mask_addr, nig_mask); in bxe_attn_int_asserted()
7624 REG_WR(sc, NIG_REG_LLH0_FUNC_EN + port*8, 0); in bxe_e1h_disable()
7632 REG_WR(sc, NIG_REG_LLH0_FUNC_EN + port*8, 1); in bxe_e1h_enable()
7800 REG_WR(sc, HC_REG_TRAILING_EDGE_0 + port*8, val); in bxe_pmf_update()
7801 REG_WR(sc, HC_REG_LEADING_EDGE_0 + port*8, val); in bxe_pmf_update()
7803 REG_WR(sc, IGU_REG_TRAILING_EDGE_LATCH, val); in bxe_pmf_update()
7804 REG_WR(sc, IGU_REG_LEADING_EDGE_LATCH, val); in bxe_pmf_update()
7922 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0); in bxe_attn_int_deasserted3()
7965 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_10, 0); in bxe_attn_int_deasserted3()
7966 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_9, 0); in bxe_attn_int_deasserted3()
7967 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_8, 0); in bxe_attn_int_deasserted3()
7968 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_7, 0); in bxe_attn_int_deasserted3()
7977 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_11, 0); in bxe_attn_int_deasserted3()
7999 REG_WR(sc, MISC_REG_AEU_CLR_LATCH_SIGNAL, 0x7ff); in bxe_attn_int_deasserted3()
8091 REG_WR(sc, reg_offset, val); in bxe_attn_int_deasserted2()
8131 REG_WR(sc, reg_offset, val); in bxe_attn_int_deasserted1()
8160 REG_WR(sc, reg_offset, val); in bxe_attn_int_deasserted0()
8178 REG_WR(sc, reg_offset, val); in bxe_attn_int_deasserted0()
8268 REG_WR(sc, reg_addr, val); in bxe_attn_int_deasserted()
8286 REG_WR(sc, reg_addr, aeu_mask); in bxe_attn_int_deasserted()
9356 REG_WR(sc, (addr + i), fill); in bxe_fill()
9375 REG_WR(sc, in bxe_wr_fp_sb_data()
9425 REG_WR(sc, in bxe_wr_sp_sb_data()
9697 REG_WR(sc, in bxe_update_rx_prod()
9735 REG_WR(sc, in bxe_init_rx_rings()
9739 REG_WR(sc, in bxe_init_rx_rings()
9832 REG_WR(sc, reg_offset, U64_LO(section)); in bxe_init_def_sb()
9833 REG_WR(sc, (reg_offset + 4), U64_HI(section)); in bxe_init_def_sb()
9835 REG_WR(sc, IGU_REG_ATTN_MSG_ADDR_L, U64_LO(section)); in bxe_init_def_sb()
9836 REG_WR(sc, IGU_REG_ATTN_MSG_ADDR_H, U64_HI(section)); in bxe_init_def_sb()
9905 REG_WR(sc, in bxe_init_internal_common()
9971 REG_WR(sc, in bxe_func_init()
10165 REG_WR(sc, in bxe_pf_init()
10171 REG_WR(sc, in bxe_pf_init()
10255 REG_WR(sc, addr, val); in bxe_hc_int_enable()
10262 REG_WR(sc, (HC_REG_INT_MASK + port*4), 0x1FFFF); in bxe_hc_int_enable()
10268 REG_WR(sc, addr, val); in bxe_hc_int_enable()
10285 REG_WR(sc, (HC_REG_TRAILING_EDGE_0 + port*8), val); in bxe_hc_int_enable()
10286 REG_WR(sc, (HC_REG_LEADING_EDGE_0 + port*8), val); in bxe_hc_int_enable()
10326 REG_WR(sc, IGU_REG_PF_CONFIGURATION, val); in bxe_igu_int_enable()
10335 REG_WR(sc, IGU_REG_PF_CONFIGURATION, val); in bxe_igu_int_enable()
10350 REG_WR(sc, IGU_REG_TRAILING_EDGE_LATCH, val); in bxe_igu_int_enable()
10351 REG_WR(sc, IGU_REG_LEADING_EDGE_LATCH, val); in bxe_igu_int_enable()
10384 REG_WR(sc, (HC_REG_INT_MASK + port*4), 0); in bxe_hc_int_disable()
10401 REG_WR(sc, addr, val); in bxe_hc_int_disable()
10421 REG_WR(sc, IGU_REG_PF_CONFIGURATION, val); in bxe_igu_int_disable()
10657 REG_WR(sc, hw_lock_control_reg + 4, resource_bit); in bxe_trylock_hw_lock()
10707 REG_WR(sc, PXP_REG_HST_DISCARD_DOORBELLS, !!close); in bxe_set_234_gates()
10709 REG_WR(sc, PXP_REG_HST_DISCARD_INTERNAL_WRITES, !!close); in bxe_set_234_gates()
10716 REG_WR(sc, HC_REG_CONFIG_1, in bxe_set_234_gates()
10721 REG_WR(sc, HC_REG_CONFIG_0, in bxe_set_234_gates()
10728 REG_WR(sc, IGU_REG_BLOCK_CONFIGURATION, in bxe_set_234_gates()
10808 REG_WR(sc, shmem + validity_offset, 0); in bxe_reset_mcp_prep()
10871 REG_WR(sc, PXP2_REG_RD_START_INIT, 0); in bxe_pxp_prep()
10872 REG_WR(sc, PXP2_REG_RQ_RBC_DONE, 0); in bxe_pxp_prep()
10968 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, in bxe_process_kill_chip_reset()
10971 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, in bxe_process_kill_chip_reset()
10977 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, in bxe_process_kill_chip_reset()
10983 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, reset_mask1); in bxe_process_kill_chip_reset()
11039 REG_WR(sc, MISC_REG_UNPREPARED, 0); in bxe_process_kill()
11067 REG_WR(sc, PGLUE_B_REG_LATCHED_ERRORS_CLR, 0x7f); in bxe_process_kill()
11906 REG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + sc->link_params.port*4, 0); in bxe_link_status_update()
14083 REG_WR(sc, PXP2_REG_PGL_ADDR_88_F0, 0); in bxe_get_device_info()
14084 REG_WR(sc, PXP2_REG_PGL_ADDR_8C_F0, 0); in bxe_get_device_info()
14085 REG_WR(sc, PXP2_REG_PGL_ADDR_90_F0, 0); in bxe_get_device_info()
14086 REG_WR(sc, PXP2_REG_PGL_ADDR_94_F0, 0); in bxe_get_device_info()
14088 REG_WR(sc, PXP2_REG_PGL_ADDR_88_F1, 0); in bxe_get_device_info()
14089 REG_WR(sc, PXP2_REG_PGL_ADDR_8C_F1, 0); in bxe_get_device_info()
14090 REG_WR(sc, PXP2_REG_PGL_ADDR_90_F1, 0); in bxe_get_device_info()
14091 REG_WR(sc, PXP2_REG_PGL_ADDR_94_F1, 0); in bxe_get_device_info()
14100 REG_WR(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1); in bxe_get_device_info()
14149 REG_WR(sc, IGU_REG_BLOCK_CONFIGURATION, val); in bxe_get_device_info()
14150 REG_WR(sc, IGU_REG_RESET_MEMORIES, 0x7f); in bxe_get_device_info()
15264 REG_WR(sc, PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR, 1 << SC_FUNC(sc)); in bxe_prev_interrupted_dmae()
15469 REG_WR(sc, vals->bmac_addr, wb_data[0]); in bxe_prev_unload_close_mac()
15470 REG_WR(sc, vals->bmac_addr + 0x4, wb_data[1]); in bxe_prev_unload_close_mac()
15476 REG_WR(sc, vals->emac_addr, 0); in bxe_prev_unload_close_mac()
15483 REG_WR(sc, base_addr + XMAC_REG_PFC_CTRL_HI, val & ~(1 << 1)); in bxe_prev_unload_close_mac()
15484 REG_WR(sc, base_addr + XMAC_REG_PFC_CTRL_HI, val | (1 << 1)); in bxe_prev_unload_close_mac()
15487 REG_WR(sc, vals->xmac_addr, 0); in bxe_prev_unload_close_mac()
15497 REG_WR(sc, vals->umac_addr, 0); in bxe_prev_unload_close_mac()
15524 REG_WR(sc, BXE_PREV_UNDI_PROD_ADDR(port), tmp_reg); in bxe_prev_unload_undi_inc()
15573 REG_WR(sc, DORQ_REG_NORM_CID_OFST, 0); in bxe_prev_unload_common()
15615 REG_WR(sc, mac_vals.xmac_addr, mac_vals.xmac_val); in bxe_prev_unload_common()
15618 REG_WR(sc, mac_vals.umac_addr, mac_vals.umac_val); in bxe_prev_unload_common()
15621 REG_WR(sc, mac_vals.emac_addr, mac_vals.emac_val); in bxe_prev_unload_common()
15624 REG_WR(sc, mac_vals.bmac_addr, mac_vals.bmac_val[0]); in bxe_prev_unload_common()
15625 REG_WR(sc, mac_vals.bmac_addr + 4, mac_vals.bmac_val[1]); in bxe_prev_unload_common()
15703 REG_WR(sc, MCP_REG_MCPR_NVM_SW_ARB, in bxe_prev_unload()
15707 REG_WR(sc, hw_lock_reg, 0xffffffff); in bxe_prev_unload()
15714 REG_WR(sc, MCP_REG_MCPR_ACCESS_LOCK, 0); in bxe_prev_unload()
16525 REG_WR(sc, igu_addr_data, data); in bxe_igu_clear_sb_gen()
16533 REG_WR(sc, igu_addr_ctl, ctl); in bxe_igu_clear_sb_gen()
16575 REG_WR(sc, (GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR), 0xd3ffff7f); in bxe_reset_common()
16582 REG_WR(sc, (GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR), val); in bxe_reset_common()
16619 REG_WR(sc, IGU_REG_PF_CONFIGURATION, val); in bxe_pf_disable()
16620 REG_WR(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0); in bxe_pf_disable()
16621 REG_WR(sc, CFC_REG_WEAK_ENABLE_PF, 0); in bxe_pf_disable()
16672 REG_WR(sc, pretend_reg, pretend_func_val); in bxe_pretend_func()
16728 REG_WR(sc, TSDM_REG_ENABLE_IN1, 0x0); in bxe_int_mem_test()
16729 REG_WR(sc, TCM_REG_PRS_IFEN, 0x0); in bxe_int_mem_test()
16730 REG_WR(sc, CFC_REG_DEBUG0, 0x1); in bxe_int_mem_test()
16731 REG_WR(sc, NIG_REG_PRS_REQ_IN_EN, 0x0); in bxe_int_mem_test()
16734 REG_WR(sc, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0); in bxe_int_mem_test()
16776 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03); in bxe_int_mem_test()
16778 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03); in bxe_int_mem_test()
16784 REG_WR(sc, TSDM_REG_ENABLE_IN1, 0x0); in bxe_int_mem_test()
16785 REG_WR(sc, TCM_REG_PRS_IFEN, 0x0); in bxe_int_mem_test()
16786 REG_WR(sc, CFC_REG_DEBUG0, 0x1); in bxe_int_mem_test()
16787 REG_WR(sc, NIG_REG_PRS_REQ_IN_EN, 0x0); in bxe_int_mem_test()
16790 REG_WR(sc, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0); in bxe_int_mem_test()
16822 REG_WR(sc, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x1); in bxe_int_mem_test()
16845 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03); in bxe_int_mem_test()
16847 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03); in bxe_int_mem_test()
16853 REG_WR(sc, PRS_REG_NIC_MODE, 1); in bxe_int_mem_test()
16857 REG_WR(sc, TSDM_REG_ENABLE_IN1, 0x7fffffff); in bxe_int_mem_test()
16858 REG_WR(sc, TCM_REG_PRS_IFEN, 0x1); in bxe_int_mem_test()
16859 REG_WR(sc, CFC_REG_DEBUG0, 0x0); in bxe_int_mem_test()
16860 REG_WR(sc, NIG_REG_PRS_REQ_IN_EN, 0x1); in bxe_int_mem_test()
16905 REG_WR(sc, MISC_REG_SPIO_INT, val); in bxe_setup_fan_failure_detection()
16910 REG_WR(sc, MISC_REG_SPIO_EVENT_EN, val); in bxe_setup_fan_failure_detection()
16918 REG_WR(sc, PXP_REG_PXP_INT_MASK_0, 0); in bxe_enable_blocks_attention()
16920 REG_WR(sc, PXP_REG_PXP_INT_MASK_1, 0x40); in bxe_enable_blocks_attention()
16922 REG_WR(sc, PXP_REG_PXP_INT_MASK_1, 0); in bxe_enable_blocks_attention()
16924 REG_WR(sc, DORQ_REG_DORQ_INT_MASK, 0); in bxe_enable_blocks_attention()
16925 REG_WR(sc, CFC_REG_CFC_INT_MASK, 0); in bxe_enable_blocks_attention()
16932 REG_WR(sc, BRB1_REG_BRB1_INT_MASK, 0xFC00); in bxe_enable_blocks_attention()
16933 REG_WR(sc, QM_REG_QM_INT_MASK, 0); in bxe_enable_blocks_attention()
16934 REG_WR(sc, TM_REG_TM_INT_MASK, 0); in bxe_enable_blocks_attention()
16935 REG_WR(sc, XSDM_REG_XSDM_INT_MASK_0, 0); in bxe_enable_blocks_attention()
16936 REG_WR(sc, XSDM_REG_XSDM_INT_MASK_1, 0); in bxe_enable_blocks_attention()
16937 REG_WR(sc, XCM_REG_XCM_INT_MASK, 0); in bxe_enable_blocks_attention()
16940 REG_WR(sc, USDM_REG_USDM_INT_MASK_0, 0); in bxe_enable_blocks_attention()
16941 REG_WR(sc, USDM_REG_USDM_INT_MASK_1, 0); in bxe_enable_blocks_attention()
16942 REG_WR(sc, UCM_REG_UCM_INT_MASK, 0); in bxe_enable_blocks_attention()
16945 REG_WR(sc, GRCBASE_UPB + PB_REG_PB_INT_MASK, 0); in bxe_enable_blocks_attention()
16946 REG_WR(sc, CSDM_REG_CSDM_INT_MASK_0, 0); in bxe_enable_blocks_attention()
16947 REG_WR(sc, CSDM_REG_CSDM_INT_MASK_1, 0); in bxe_enable_blocks_attention()
16948 REG_WR(sc, CCM_REG_CCM_INT_MASK, 0); in bxe_enable_blocks_attention()
16959 REG_WR(sc, PXP2_REG_PXP2_INT_MASK_0, val); in bxe_enable_blocks_attention()
16961 REG_WR(sc, TSDM_REG_TSDM_INT_MASK_0, 0); in bxe_enable_blocks_attention()
16962 REG_WR(sc, TSDM_REG_TSDM_INT_MASK_1, 0); in bxe_enable_blocks_attention()
16963 REG_WR(sc, TCM_REG_TCM_INT_MASK, 0); in bxe_enable_blocks_attention()
16968 REG_WR(sc, TSEM_REG_TSEM_INT_MASK_1, 0x07ff); in bxe_enable_blocks_attention()
16971 REG_WR(sc, CDU_REG_CDU_INT_MASK, 0); in bxe_enable_blocks_attention()
16972 REG_WR(sc, DMAE_REG_DMAE_INT_MASK, 0); in bxe_enable_blocks_attention()
16974 REG_WR(sc, PBF_REG_PBF_INT_MASK, 0x18); /* bit 3,4 masked */ in bxe_enable_blocks_attention()
16999 REG_WR(sc, (GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET), 0xffffffff); in bxe_init_hw_common()
17007 REG_WR(sc, (GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET), val); in bxe_init_hw_common()
17025 REG_WR(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1); in bxe_init_hw_common()
17047 REG_WR(sc, PXP_REG_PXP_INT_MASK_0, 0); in bxe_init_hw_common()
17054 REG_WR(sc, PXP2_REG_RQ_QM_ENDIAN_M, 1); in bxe_init_hw_common()
17055 REG_WR(sc, PXP2_REG_RQ_TM_ENDIAN_M, 1); in bxe_init_hw_common()
17056 REG_WR(sc, PXP2_REG_RQ_SRC_ENDIAN_M, 1); in bxe_init_hw_common()
17057 REG_WR(sc, PXP2_REG_RQ_CDU_ENDIAN_M, 1); in bxe_init_hw_common()
17058 REG_WR(sc, PXP2_REG_RQ_DBG_ENDIAN_M, 1); in bxe_init_hw_common()
17060 REG_WR(sc, PXP2_REG_RQ_HC_ENDIAN_M, 0); in bxe_init_hw_common()
17063 REG_WR(sc, PXP2_REG_RD_QM_SWAP_MODE, 1); in bxe_init_hw_common()
17064 REG_WR(sc, PXP2_REG_RD_TM_SWAP_MODE, 1); in bxe_init_hw_common()
17065 REG_WR(sc, PXP2_REG_RD_SRC_SWAP_MODE, 1); in bxe_init_hw_common()
17066 REG_WR(sc, PXP2_REG_RD_CDURD_SWAP_MODE, 1); in bxe_init_hw_common()
17072 REG_WR(sc, PXP2_REG_PGL_TAGS_LIMIT, 0x1); in bxe_init_hw_common()
17190 REG_WR(sc, PXP2_REG_RQ_DRAM_ALIGN, BXE_PXP_DRAM_ALIGN); in bxe_init_hw_common()
17191 REG_WR(sc, PXP2_REG_RQ_DRAM_ALIGN_RD, BXE_PXP_DRAM_ALIGN); in bxe_init_hw_common()
17192 REG_WR(sc, PXP2_REG_RQ_DRAM_ALIGN_SEL, 1); in bxe_init_hw_common()
17195 REG_WR(sc, PXP2_REG_RQ_DISABLE_INPUTS, 0); in bxe_init_hw_common()
17196 REG_WR(sc, PXP2_REG_RD_DISABLE_INPUTS, 0); in bxe_init_hw_common()
17246 REG_WR(sc, QM_REG_SOFT_RESET, 1); in bxe_init_hw_common()
17247 REG_WR(sc, QM_REG_SOFT_RESET, 0); in bxe_init_hw_common()
17253 REG_WR(sc, DORQ_REG_DPM_CID_OFST, BXE_DB_SHIFT); in bxe_init_hw_common()
17256 REG_WR(sc, DORQ_REG_DORQ_INT_MASK, 0); in bxe_init_hw_common()
17262 REG_WR(sc, PRS_REG_A_PRSU_20, 0xf); in bxe_init_hw_common()
17265 REG_WR(sc, PRS_REG_E1HOV_MODE, sc->devinfo.mf_info.path_has_ovlan); in bxe_init_hw_common()
17274 REG_WR(sc, PRS_REG_HDRS_AFTER_BASIC, 0xE); in bxe_init_hw_common()
17275 REG_WR(sc, PRS_REG_MUST_HAVE_HDRS, 0xA); in bxe_init_hw_common()
17276 REG_WR(sc, PRS_REG_HDRS_AFTER_TAG_0, 0x6); in bxe_init_hw_common()
17277 REG_WR(sc, PRS_REG_TAG_ETHERTYPE_0, 0x8926); in bxe_init_hw_common()
17278 REG_WR(sc, PRS_REG_TAG_LEN_0, 0x4); in bxe_init_hw_common()
17284 REG_WR(sc, PRS_REG_HDRS_AFTER_BASIC, in bxe_init_hw_common()
17296 REG_WR(sc, TSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST, in bxe_init_hw_common()
17299 REG_WR(sc, XSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST, in bxe_init_hw_common()
17312 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, in bxe_init_hw_common()
17314 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, in bxe_init_hw_common()
17327 REG_WR(sc, PBF_REG_HDRS_AFTER_BASIC, 0xE); in bxe_init_hw_common()
17328 REG_WR(sc, PBF_REG_MUST_HAVE_HDRS, 0xA); in bxe_init_hw_common()
17329 REG_WR(sc, PBF_REG_HDRS_AFTER_TAG_0, 0x6); in bxe_init_hw_common()
17330 REG_WR(sc, PBF_REG_TAG_ETHERTYPE_0, 0x8926); in bxe_init_hw_common()
17331 REG_WR(sc, PBF_REG_TAG_LEN_0, 0x4); in bxe_init_hw_common()
17333 REG_WR(sc, PBF_REG_HDRS_AFTER_BASIC, in bxe_init_hw_common()
17338 REG_WR(sc, SRC_REG_SOFT_RST, 1); in bxe_init_hw_common()
17343 REG_WR(sc, SRC_REG_KEYSEARCH_0, 0x63285672); in bxe_init_hw_common()
17344 REG_WR(sc, SRC_REG_KEYSEARCH_1, 0x24b8f2cc); in bxe_init_hw_common()
17345 REG_WR(sc, SRC_REG_KEYSEARCH_2, 0x223aef9b); in bxe_init_hw_common()
17346 REG_WR(sc, SRC_REG_KEYSEARCH_3, 0x26001e3a); in bxe_init_hw_common()
17347 REG_WR(sc, SRC_REG_KEYSEARCH_4, 0x7ae91116); in bxe_init_hw_common()
17348 REG_WR(sc, SRC_REG_KEYSEARCH_5, 0x5ce5230b); in bxe_init_hw_common()
17349 REG_WR(sc, SRC_REG_KEYSEARCH_6, 0x298d8adf); in bxe_init_hw_common()
17350 REG_WR(sc, SRC_REG_KEYSEARCH_7, 0x6eb0ff09); in bxe_init_hw_common()
17351 REG_WR(sc, SRC_REG_KEYSEARCH_8, 0x1830f82f); in bxe_init_hw_common()
17352 REG_WR(sc, SRC_REG_KEYSEARCH_9, 0x01e46be7); in bxe_init_hw_common()
17354 REG_WR(sc, SRC_REG_SOFT_RST, 0); in bxe_init_hw_common()
17364 REG_WR(sc, CDU_REG_CDU_GLOBAL_PARAMS, val); in bxe_init_hw_common()
17368 REG_WR(sc, CFC_REG_INIT_REG, 0x7FF); in bxe_init_hw_common()
17370 REG_WR(sc, CFC_REG_CFC_INT_MASK, 0); in bxe_init_hw_common()
17373 REG_WR(sc, CFC_REG_DEBUG0, 0x20020000); in bxe_init_hw_common()
17377 REG_WR(sc, IGU_REG_RESET_MEMORIES, 0x36); in bxe_init_hw_common()
17384 REG_WR(sc, 0x2814, 0xffffffff); in bxe_init_hw_common()
17385 REG_WR(sc, 0x3820, 0xffffffff); in bxe_init_hw_common()
17388 REG_WR(sc, PCICFG_OFFSET + PXPCS_TL_CONTROL_5, in bxe_init_hw_common()
17391 REG_WR(sc, PCICFG_OFFSET + PXPCS_TL_FUNC345_STAT, in bxe_init_hw_common()
17395 REG_WR(sc, PCICFG_OFFSET + PXPCS_TL_FUNC678_STAT, in bxe_init_hw_common()
17406 REG_WR(sc, NIG_REG_LLH_MF_MODE, IS_MF(sc)); in bxe_init_hw_common()
17411 REG_WR(sc, NIG_REG_LLH_E1HOV_MODE, IS_MF_SD(sc)); in bxe_init_hw_common()
17434 REG_WR(sc, CFC_REG_DEBUG0, 0); in bxe_init_hw_common()
17501 REG_WR(sc, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0); in bxe_init_hw_port()
17514 REG_WR(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1); in bxe_init_hw_port()
17532 REG_WR(sc, TM_REG_LIN0_SCAN_TIME + port*4, 20); in bxe_init_hw_port()
17533 REG_WR(sc, TM_REG_LIN0_MAX_ACTIVE_CID + port*4, 31); in bxe_init_hw_port()
17555 REG_WR(sc, BRB1_REG_PAUSE_LOW_THRESHOLD_0 + port*4, low); in bxe_init_hw_port()
17556 REG_WR(sc, BRB1_REG_PAUSE_HIGH_THRESHOLD_0 + port*4, high); in bxe_init_hw_port()
17560 REG_WR(sc, SC_PORT(sc) ? in bxe_init_hw_port()
17569 REG_WR(sc, SC_PORT(sc) ? in bxe_init_hw_port()
17572 REG_WR(sc, SC_PORT(sc) ? in bxe_init_hw_port()
17575 REG_WR(sc, SC_PORT(sc) ? in bxe_init_hw_port()
17583 REG_WR(sc, SC_PORT(sc) ? in bxe_init_hw_port()
17607 REG_WR(sc, PBF_REG_P0_PAUSE_ENABLE + port*4, 0); in bxe_init_hw_port()
17610 REG_WR(sc, PBF_REG_P0_ARB_THRSH + port*4, (9040/16)); in bxe_init_hw_port()
17612 REG_WR(sc, PBF_REG_P0_INIT_CRD + port*4, (9040/16) + 553 - 22); in bxe_init_hw_port()
17615 REG_WR(sc, PBF_REG_INIT_P0 + port*4, 1); in bxe_init_hw_port()
17617 REG_WR(sc, PBF_REG_INIT_P0 + port*4, 0); in bxe_init_hw_port()
17628 REG_WR(sc, HC_REG_LEADING_EDGE_0 + port*8, 0); in bxe_init_hw_port()
17629 REG_WR(sc, HC_REG_TRAILING_EDGE_0 + port*8, 0); in bxe_init_hw_port()
17643 REG_WR(sc, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, val); in bxe_init_hw_port()
17652 REG_WR(sc, SC_PORT(sc) ? in bxe_init_hw_port()
17656 REG_WR(sc, SC_PORT(sc) ? in bxe_init_hw_port()
17663 REG_WR(sc, SC_PORT(sc) ? in bxe_init_hw_port()
17669 REG_WR(sc, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 1); in bxe_init_hw_port()
17674 REG_WR(sc, NIG_REG_LLH0_BRB1_DRV_MASK_MF + port*4, in bxe_init_hw_port()
17689 REG_WR(sc, (SC_PORT(sc) ? NIG_REG_LLH1_CLS_TYPE : in bxe_init_hw_port()
17692 REG_WR(sc, NIG_REG_LLFC_ENABLE_0 + port*4, 0); in bxe_init_hw_port()
17693 REG_WR(sc, NIG_REG_LLFC_OUT_EN_0 + port*4, 0); in bxe_init_hw_port()
17694 REG_WR(sc, NIG_REG_PAUSE_ENABLE_0 + port*4, 1); in bxe_init_hw_port()
17704 REG_WR(sc, reg_addr, val); in bxe_init_hw_port()
17840 REG_WR(sc, XSDM_REG_OPERATION_GEN, op_gen_command); in bxe_send_final_clnup()
17851 REG_WR(sc, comp_addr, 0); in bxe_send_final_clnup()
18028 REG_WR(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1); in bxe_pf_flr_clnup()
18063 REG_WR(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1); in bxe_pf_flr_clnup()
18098 REG_WR(sc, addr, val); in bxe_init_hw_func()
18116 REG_WR(sc, PRS_REG_NIC_MODE, 1); in bxe_init_hw_func()
18142 REG_WR(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1); in bxe_init_hw_func()
18144 REG_WR(sc, IGU_REG_PF_CONFIGURATION, pf_conf); in bxe_init_hw_func()
18152 REG_WR(sc, PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR, func); in bxe_init_hw_func()
18169 REG_WR(sc, QM_REG_PF_EN, 1); in bxe_init_hw_func()
18172 REG_WR(sc, TSEM_REG_VFPF_ERR_NUM, BXE_MAX_NUM_OF_VFS + func); in bxe_init_hw_func()
18173 REG_WR(sc, USEM_REG_VFPF_ERR_NUM, BXE_MAX_NUM_OF_VFS + func); in bxe_init_hw_func()
18174 REG_WR(sc, CSEM_REG_VFPF_ERR_NUM, BXE_MAX_NUM_OF_VFS + func); in bxe_init_hw_func()
18175 REG_WR(sc, XSEM_REG_VFPF_ERR_NUM, BXE_MAX_NUM_OF_VFS + func); in bxe_init_hw_func()
18194 REG_WR(sc, PBF_REG_DISABLE_PF, 0); in bxe_init_hw_func()
18201 REG_WR(sc, CFC_REG_WEAK_ENABLE_PF, 1); in bxe_init_hw_func()
18204 REG_WR(sc, NIG_REG_LLH0_FUNC_EN + port*8, 1); in bxe_init_hw_func()
18205 REG_WR(sc, NIG_REG_LLH0_FUNC_VLAN_ID + port*8, OVLAN(sc)); in bxe_init_hw_func()
18213 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0); in bxe_init_hw_func()
18215 REG_WR(sc, HC_REG_LEADING_EDGE_0 + port*8, 0); in bxe_init_hw_func()
18216 REG_WR(sc, HC_REG_TRAILING_EDGE_0 + port*8, 0); in bxe_init_hw_func()
18223 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0); in bxe_init_hw_func()
18226 REG_WR(sc, IGU_REG_LEADING_EDGE_LATCH, 0); in bxe_init_hw_func()
18227 REG_WR(sc, IGU_REG_TRAILING_EDGE_LATCH, 0); in bxe_init_hw_func()
18264 REG_WR(sc, addr, 0); in bxe_init_hw_func()
18293 REG_WR(sc, addr, 0); in bxe_init_hw_func()
18317 REG_WR(sc, IGU_REG_SB_INT_BEFORE_MASK_LSB, 0); in bxe_init_hw_func()
18318 REG_WR(sc, IGU_REG_SB_INT_BEFORE_MASK_MSB, 0); in bxe_init_hw_func()
18319 REG_WR(sc, IGU_REG_SB_MASK_LSB, 0); in bxe_init_hw_func()
18320 REG_WR(sc, IGU_REG_SB_MASK_MSB, 0); in bxe_init_hw_func()
18321 REG_WR(sc, IGU_REG_PBA_STATUS_LSB, 0); in bxe_init_hw_func()
18322 REG_WR(sc, IGU_REG_PBA_STATUS_MSB, 0); in bxe_init_hw_func()
18327 REG_WR(sc, 0x2114, 0xffffffff); in bxe_init_hw_func()
18328 REG_WR(sc, 0x2120, 0xffffffff); in bxe_init_hw_func()
18397 REG_WR(sc, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0); in bxe_reset_port()
18400 REG_WR(sc, NIG_REG_LLH0_BRB1_DRV_MASK + port*4, 0x0); in bxe_reset_port()
18402 REG_WR(sc, (port ? NIG_REG_LLH1_BRB1_NOT_MCP : in bxe_reset_port()
18406 REG_WR(sc, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, 0); in bxe_reset_port()
18477 REG_WR(sc, BAR_XSTRORM_INTMEM + XSTORM_SPQ_DATA_OFFSET(func), 0); in bxe_reset_func()
18482 REG_WR(sc, HC_REG_LEADING_EDGE_0 + port*8, 0); in bxe_reset_func()
18483 REG_WR(sc, HC_REG_TRAILING_EDGE_0 + port*8, 0); in bxe_reset_func()
18485 REG_WR(sc, IGU_REG_LEADING_EDGE_LATCH, 0); in bxe_reset_func()
18486 REG_WR(sc, IGU_REG_TRAILING_EDGE_LATCH, 0); in bxe_reset_func()
18491 REG_WR(sc, TM_REG_EN_LINEAR0_TIMER + port*4, 0); in bxe_reset_func()
18603 REG_WR(sc, addr + (i * 4), data[i]); in ecore_storm_memset_struct()
18805 REG_WR(sc, write_addr[j], page_addr[i]); in bxe_read_pages_regs()
19364 REG_WR(sc, reg_rdw_p->reg_id, reg_rdw_p->reg_val); in bxe_eioctl()