Lines Matching refs:OP_IF_MODE_AND
61 {OP_IF_MODE_AND, 1, 0x8}, /* e2 */
63 {OP_IF_MODE_AND, 1, 0x10}, /* e3 */
65 {OP_IF_MODE_AND, 1, 0x8}, /* e2 */
67 {OP_IF_MODE_AND, 1, 0x10}, /* e3 */
69 {OP_IF_MODE_AND, 1, 0x2000}, /* e3_b0 */
71 {OP_IF_MODE_AND, 4, 0x2020}, /* e3_b0+port2 */
76 {OP_IF_MODE_AND, 3, 0x2040}, /* e3_b0+port4 */
83 {OP_IF_MODE_AND, 1, 0x8}, /* e2 */
85 {OP_IF_MODE_AND, 2, 0x2020}, /* e3_b0+port2 */
88 {OP_IF_MODE_AND, 2, 0x2040}, /* e3_b0+port4 */
93 {OP_IF_MODE_AND, 2, 0x2040}, /* e3_b0+port4 */
113 {OP_IF_MODE_AND, 1, 0x8}, /* e2 */
153 {OP_IF_MODE_AND, 1, 0x8}, /* e2 */
210 {OP_IF_MODE_AND, 1, 0x9}, /* asic+e2 */
212 {OP_IF_MODE_AND, 1, 0xa}, /* fpga+e2 */
214 {OP_IF_MODE_AND, 1, 0xc}, /* emul+e2 */
216 {OP_IF_MODE_AND, 1, 0x1001}, /* asic+e3_a0 */
218 {OP_IF_MODE_AND, 1, 0x1002}, /* fpga+e3_a0 */
220 {OP_IF_MODE_AND, 1, 0x1004}, /* emul+e3_a0 */
222 {OP_IF_MODE_AND, 1, 0x2001}, /* asic+e3_b0 */
224 {OP_IF_MODE_AND, 1, 0x2002}, /* fpga+e3_b0 */
226 {OP_IF_MODE_AND, 1, 0x2004}, /* emul+e3_b0 */
515 {OP_IF_MODE_AND, 2, 0x8}, /* e2 */
518 {OP_IF_MODE_AND, 2, 0x9}, /* asic+e2 */
521 {OP_IF_MODE_AND, 2, 0xa}, /* fpga+e2 */
524 {OP_IF_MODE_AND, 2, 0xc}, /* emul+e2 */
527 {OP_IF_MODE_AND, 2, 0x1000}, /* e3_a0 */
530 {OP_IF_MODE_AND, 2, 0x1001}, /* asic+e3_a0 */
533 {OP_IF_MODE_AND, 2, 0x1002}, /* fpga+e3_a0 */
536 {OP_IF_MODE_AND, 2, 0x1004}, /* emul+e3_a0 */
539 {OP_IF_MODE_AND, 2, 0x2000}, /* e3_b0 */
542 {OP_IF_MODE_AND, 2, 0x2001}, /* asic+e3_b0 */
545 {OP_IF_MODE_AND, 2, 0x2002}, /* fpga+e3_b0 */
548 {OP_IF_MODE_AND, 2, 0x2004}, /* emul+e3_b0 */
553 {OP_IF_MODE_AND, 1, 0x2}, /* fpga */
555 {OP_IF_MODE_AND, 1, 0x4}, /* emul */
557 {OP_IF_MODE_AND, 1, 0x11}, /* e3+asic */
559 {OP_IF_MODE_AND, 1, 0x8}, /* e2 */
561 {OP_IF_MODE_AND, 4, 0x10}, /* e3 */
566 {OP_IF_MODE_AND, 1, 0x11}, /* e3+asic */
581 {OP_IF_MODE_AND, 1, 0x10}, /* e3 */
658 {OP_IF_MODE_AND, 1, 0x8}, /* e2 */
660 {OP_IF_MODE_AND, 1, 0x10}, /* e3 */
697 {OP_IF_MODE_AND, 1, 0x8}, /* e2 */
742 {OP_IF_MODE_AND, 1, 0x88}, /* e2+sf */
744 {OP_IF_MODE_AND, 1, 0x108}, /* e2+mf */
748 {OP_IF_MODE_AND, 1, 0x90}, /* e3+sf */
750 {OP_IF_MODE_AND, 1, 0x110}, /* e3+mf */
754 {OP_IF_MODE_AND, 1, 0x90}, /* e3+sf */
756 {OP_IF_MODE_AND, 1, 0x110}, /* e3+mf */
785 {OP_IF_MODE_AND, 1, 0x2200}, /* e3_b0+mf_sd */
812 {OP_IF_MODE_AND, 2, 0x8}, /* e2 */
815 {OP_IF_MODE_AND, 1, 0x80}, /* sf */
817 {OP_IF_MODE_AND, 1, 0x200}, /* mf_sd */
819 {OP_IF_MODE_AND, 1, 0x400}, /* mf_si */
821 {OP_IF_MODE_AND, 1, 0x800}, /* mf_afex */
823 {OP_IF_MODE_AND, 4, 0x2000}, /* e3_b0 */
851 {OP_IF_MODE_AND, 2, 0x8}, /* e2 */
854 {OP_IF_MODE_AND, 1, 0x80}, /* sf */
856 {OP_IF_MODE_AND, 1, 0x200}, /* mf_sd */
858 {OP_IF_MODE_AND, 1, 0x400}, /* mf_si */
860 {OP_IF_MODE_AND, 1, 0x800}, /* mf_afex */
862 {OP_IF_MODE_AND, 4, 0x2000}, /* e3_b0 */
898 {OP_IF_MODE_AND, 1, 0x2200}, /* e3_b0+mf_sd */
904 {OP_IF_MODE_AND, 1, 0x2000}, /* e3_b0 */
911 {OP_IF_MODE_AND, 4, 0x2000}, /* e3_b0 */
918 {OP_IF_MODE_AND, 1, 0x2000}, /* e3_b0 */
979 {OP_IF_MODE_AND, 1, 0x2200}, /* e3_b0+mf_sd */
1055 {OP_IF_MODE_AND, 20, 0x8}, /* e2 */
1076 {OP_IF_MODE_AND, 28, 0x1000}, /* e3_a0 */
1105 {OP_IF_MODE_AND, 14, 0x1020}, /* e3_a0+port2 */
1120 {OP_IF_MODE_AND, 14, 0x1040}, /* e3_a0+port4 */
1135 {OP_IF_MODE_AND, 7, 0x2000}, /* e3_b0 */
1143 {OP_IF_MODE_AND, 15, 0x4020}, /* cos3+port2 */
1159 {OP_IF_MODE_AND, 13, 0x4040}, /* cos3+port4 */
1173 {OP_IF_MODE_AND, 13, 0x8000}, /* cos6 */
1207 {OP_IF_MODE_AND, 2, 0x8}, /* e2 */
1210 {OP_IF_MODE_AND, 2, 0x10}, /* e3 */
1251 {OP_IF_MODE_AND, 1, 0x9}, /* asic+e2 */
1253 {OP_IF_MODE_AND, 1, 0xa}, /* fpga+e2 */
1255 {OP_IF_MODE_AND, 1, 0xc}, /* emul+e2 */
1257 {OP_IF_MODE_AND, 1, 0x1001}, /* asic+e3_a0 */
1259 {OP_IF_MODE_AND, 1, 0x1002}, /* fpga+e3_a0 */
1261 {OP_IF_MODE_AND, 1, 0x1004}, /* emul+e3_a0 */
1263 {OP_IF_MODE_AND, 1, 0x2001}, /* asic+e3_b0 */
1265 {OP_IF_MODE_AND, 1, 0x2002}, /* fpga+e3_b0 */
1267 {OP_IF_MODE_AND, 1, 0x2004}, /* emul+e3_b0 */
1306 {OP_IF_MODE_AND, 1, 0x9}, /* asic+e2 */
1308 {OP_IF_MODE_AND, 1, 0xa}, /* fpga+e2 */
1310 {OP_IF_MODE_AND, 1, 0xc}, /* emul+e2 */
1312 {OP_IF_MODE_AND, 1, 0x1001}, /* asic+e3_a0 */
1314 {OP_IF_MODE_AND, 1, 0x1002}, /* fpga+e3_a0 */
1316 {OP_IF_MODE_AND, 1, 0x1004}, /* emul+e3_a0 */
1318 {OP_IF_MODE_AND, 1, 0x2001}, /* asic+e3_b0 */
1320 {OP_IF_MODE_AND, 1, 0x2002}, /* fpga+e3_b0 */
1322 {OP_IF_MODE_AND, 1, 0x2004}, /* emul+e3_b0 */
1344 {OP_IF_MODE_AND, 3, 0x8}, /* e2 */
1348 {OP_IF_MODE_AND, 2, 0x9}, /* asic+e2 */
1351 {OP_IF_MODE_AND, 2, 0xa}, /* fpga+e2 */
1354 {OP_IF_MODE_AND, 2, 0xc}, /* emul+e2 */
1357 {OP_IF_MODE_AND, 1, 0x20}, /* port2 */
1359 {OP_IF_MODE_AND, 1, 0x40}, /* port4 */
1361 {OP_IF_MODE_AND, 3, 0x1000}, /* e3_a0 */
1365 {OP_IF_MODE_AND, 2, 0x1001}, /* asic+e3_a0 */
1368 {OP_IF_MODE_AND, 2, 0x1002}, /* fpga+e3_a0 */
1371 {OP_IF_MODE_AND, 2, 0x1004}, /* emul+e3_a0 */
1374 {OP_IF_MODE_AND, 3, 0x2000}, /* e3_b0 */
1378 {OP_IF_MODE_AND, 2, 0x2001}, /* asic+e3_b0 */
1381 {OP_IF_MODE_AND, 2, 0x2002}, /* fpga+e3_b0 */
1384 {OP_IF_MODE_AND, 2, 0x2004}, /* emul+e3_b0 */
1387 {OP_IF_MODE_AND, 1, 0x4000}, /* cos3 */
1389 {OP_IF_MODE_AND, 1, 0x8000}, /* cos6 */
1394 {OP_IF_MODE_AND, 1, 0x2}, /* fpga */
1396 {OP_IF_MODE_AND, 1, 0x4}, /* emul */
1398 {OP_IF_MODE_AND, 1, 0x11}, /* e3+asic */
1400 {OP_IF_MODE_AND, 2, 0x8}, /* e2 */
1403 {OP_IF_MODE_AND, 7, 0x10}, /* e3 */
1412 {OP_IF_MODE_AND, 1, 0x11}, /* e3+asic */
1427 {OP_IF_MODE_AND, 1, 0x10}, /* e3 */
1530 {OP_IF_MODE_AND, 1, 0x8}, /* e2 */
1587 {OP_IF_MODE_AND, 1, 0x9}, /* asic+e2 */
1589 {OP_IF_MODE_AND, 1, 0xa}, /* fpga+e2 */
1591 {OP_IF_MODE_AND, 1, 0xc}, /* emul+e2 */
1593 {OP_IF_MODE_AND, 1, 0x1001}, /* asic+e3_a0 */
1595 {OP_IF_MODE_AND, 1, 0x1002}, /* fpga+e3_a0 */
1597 {OP_IF_MODE_AND, 1, 0x1004}, /* emul+e3_a0 */
1599 {OP_IF_MODE_AND, 1, 0x2001}, /* asic+e3_b0 */
1601 {OP_IF_MODE_AND, 1, 0x2002}, /* fpga+e3_b0 */
1603 {OP_IF_MODE_AND, 1, 0x2004}, /* emul+e3_b0 */
1621 {OP_IF_MODE_AND, 2, 0x8}, /* e2 */
1624 {OP_IF_MODE_AND, 2, 0x9}, /* asic+e2 */
1627 {OP_IF_MODE_AND, 2, 0xa}, /* fpga+e2 */
1630 {OP_IF_MODE_AND, 2, 0xc}, /* emul+e2 */
1633 {OP_IF_MODE_AND, 2, 0x1000}, /* e3_a0 */
1636 {OP_IF_MODE_AND, 2, 0x1001}, /* asic+e3_a0 */
1639 {OP_IF_MODE_AND, 2, 0x1002}, /* fpga+e3_a0 */
1642 {OP_IF_MODE_AND, 2, 0x1004}, /* emul+e3_a0 */
1645 {OP_IF_MODE_AND, 2, 0x2000}, /* e3_b0 */
1648 {OP_IF_MODE_AND, 2, 0x2001}, /* asic+e3_b0 */
1651 {OP_IF_MODE_AND, 2, 0x2002}, /* fpga+e3_b0 */
1654 {OP_IF_MODE_AND, 2, 0x2004}, /* emul+e3_b0 */
1659 {OP_IF_MODE_AND, 1, 0x2}, /* fpga */
1661 {OP_IF_MODE_AND, 1, 0x4}, /* emul */
1663 {OP_IF_MODE_AND, 1, 0x11}, /* e3+asic */
1665 {OP_IF_MODE_AND, 1, 0x8}, /* e2 */
1667 {OP_IF_MODE_AND, 4, 0x10}, /* e3 */
1672 {OP_IF_MODE_AND, 1, 0x11}, /* e3+asic */
1687 {OP_IF_MODE_AND, 1, 0x10}, /* e3 */
1904 {OP_IF_MODE_AND, 1, 0x9}, /* asic+e2 */
1906 {OP_IF_MODE_AND, 1, 0xa}, /* fpga+e2 */
1908 {OP_IF_MODE_AND, 1, 0xc}, /* emul+e2 */
1910 {OP_IF_MODE_AND, 1, 0x1001}, /* asic+e3_a0 */
1912 {OP_IF_MODE_AND, 1, 0x1002}, /* fpga+e3_a0 */
1914 {OP_IF_MODE_AND, 1, 0x1004}, /* emul+e3_a0 */
1916 {OP_IF_MODE_AND, 1, 0x2001}, /* asic+e3_b0 */
1918 {OP_IF_MODE_AND, 1, 0x2002}, /* fpga+e3_b0 */
1920 {OP_IF_MODE_AND, 1, 0x2004}, /* emul+e3_b0 */
1941 {OP_IF_MODE_AND, 3, 0x8}, /* e2 */
1945 {OP_IF_MODE_AND, 2, 0x9}, /* asic+e2 */
1948 {OP_IF_MODE_AND, 2, 0xa}, /* fpga+e2 */
1951 {OP_IF_MODE_AND, 2, 0xc}, /* emul+e2 */
1954 {OP_IF_MODE_AND, 3, 0x20}, /* port2 */
1958 {OP_IF_MODE_AND, 2, 0x40}, /* port4 */
1961 {OP_IF_MODE_AND, 3, 0x1000}, /* e3_a0 */
1965 {OP_IF_MODE_AND, 2, 0x1001}, /* asic+e3_a0 */
1968 {OP_IF_MODE_AND, 2, 0x1002}, /* fpga+e3_a0 */
1971 {OP_IF_MODE_AND, 2, 0x1004}, /* emul+e3_a0 */
1974 {OP_IF_MODE_AND, 3, 0x2000}, /* e3_b0 */
1978 {OP_IF_MODE_AND, 2, 0x2001}, /* asic+e3_b0 */
1981 {OP_IF_MODE_AND, 2, 0x2002}, /* fpga+e3_b0 */
1984 {OP_IF_MODE_AND, 2, 0x2004}, /* emul+e3_b0 */
1987 {OP_IF_MODE_AND, 1, 0x4000}, /* cos3 */
1989 {OP_IF_MODE_AND, 1, 0x8000}, /* cos6 */
1994 {OP_IF_MODE_AND, 1, 0x2}, /* fpga */
1996 {OP_IF_MODE_AND, 1, 0x4}, /* emul */
1998 {OP_IF_MODE_AND, 1, 0x11}, /* e3+asic */
2000 {OP_IF_MODE_AND, 2, 0x8}, /* e2 */
2003 {OP_IF_MODE_AND, 7, 0x10}, /* e3 */
2012 {OP_IF_MODE_AND, 1, 0x11}, /* e3+asic */
2027 {OP_IF_MODE_AND, 1, 0x10}, /* e3 */