420     struct cpu_reg *, struct fw_info *);
421 static void bce_start_cpu			(struct bce_softc *, struct cpu_reg *);
422 static void bce_halt_cpu			(struct bce_softc *, struct cpu_reg *);
3970 bce_load_cpu_fw(struct bce_softc *sc, struct cpu_reg *cpu_reg,  in bce_load_cpu_fw()  argument
3977     bce_halt_cpu(sc, cpu_reg);  in bce_load_cpu_fw()
3980 	offset = cpu_reg->spad_base + (fw->text_addr - cpu_reg->mips_view_base);  in bce_load_cpu_fw()
3990 	offset = cpu_reg->spad_base + (fw->data_addr - cpu_reg->mips_view_base);  in bce_load_cpu_fw()
4000 	offset = cpu_reg->spad_base + (fw->sbss_addr - cpu_reg->mips_view_base);  in bce_load_cpu_fw()
4010 	offset = cpu_reg->spad_base + (fw->bss_addr - cpu_reg->mips_view_base);  in bce_load_cpu_fw()
4020 	offset = cpu_reg->spad_base +  in bce_load_cpu_fw()
4021 		(fw->rodata_addr - cpu_reg->mips_view_base);  in bce_load_cpu_fw()
4031 	REG_WR_IND(sc, cpu_reg->inst, 0);  in bce_load_cpu_fw()
4032 	REG_WR_IND(sc, cpu_reg->pc, fw->start_addr);  in bce_load_cpu_fw()
4046 bce_start_cpu(struct bce_softc *sc, struct cpu_reg *cpu_reg)  in bce_start_cpu()  argument
4053 	val = REG_RD_IND(sc, cpu_reg->mode);  in bce_start_cpu()
4054 	val &= ~cpu_reg->mode_value_halt;  in bce_start_cpu()
4055 	REG_WR_IND(sc, cpu_reg->state, cpu_reg->state_value_clear);  in bce_start_cpu()
4056 	REG_WR_IND(sc, cpu_reg->mode, val);  in bce_start_cpu()
4068 bce_halt_cpu(struct bce_softc *sc, struct cpu_reg *cpu_reg)  in bce_halt_cpu()  argument
4075 	val = REG_RD_IND(sc, cpu_reg->mode);  in bce_halt_cpu()
4076 	val |= cpu_reg->mode_value_halt;  in bce_halt_cpu()
4077 	REG_WR_IND(sc, cpu_reg->mode, val);  in bce_halt_cpu()
4078 	REG_WR_IND(sc, cpu_reg->state, cpu_reg->state_value_clear);  in bce_halt_cpu()
4092 	struct cpu_reg cpu_reg;  in bce_start_rxp_cpu()  local
4096 	cpu_reg.mode = BCE_RXP_CPU_MODE;  in bce_start_rxp_cpu()
4097 	cpu_reg.mode_value_halt = BCE_RXP_CPU_MODE_SOFT_HALT;  in bce_start_rxp_cpu()
4098 	cpu_reg.mode_value_sstep = BCE_RXP_CPU_MODE_STEP_ENA;  in bce_start_rxp_cpu()
4099 	cpu_reg.state = BCE_RXP_CPU_STATE;  in bce_start_rxp_cpu()
4100 	cpu_reg.state_value_clear = 0xffffff;  in bce_start_rxp_cpu()
4101 	cpu_reg.gpr0 = BCE_RXP_CPU_REG_FILE;  in bce_start_rxp_cpu()
4102 	cpu_reg.evmask = BCE_RXP_CPU_EVENT_MASK;  in bce_start_rxp_cpu()
4103 	cpu_reg.pc = BCE_RXP_CPU_PROGRAM_COUNTER;  in bce_start_rxp_cpu()
4104 	cpu_reg.inst = BCE_RXP_CPU_INSTRUCTION;  in bce_start_rxp_cpu()
4105 	cpu_reg.bp = BCE_RXP_CPU_HW_BREAKPOINT;  in bce_start_rxp_cpu()
4106 	cpu_reg.spad_base = BCE_RXP_SCRATCH;  in bce_start_rxp_cpu()
4107 	cpu_reg.mips_view_base = 0x8000000;  in bce_start_rxp_cpu()
4110 	bce_start_cpu(sc, &cpu_reg);  in bce_start_rxp_cpu()
4124 	struct cpu_reg cpu_reg;  in bce_init_rxp_cpu()  local
4129 	cpu_reg.mode = BCE_RXP_CPU_MODE;  in bce_init_rxp_cpu()
4130 	cpu_reg.mode_value_halt = BCE_RXP_CPU_MODE_SOFT_HALT;  in bce_init_rxp_cpu()
4131 	cpu_reg.mode_value_sstep = BCE_RXP_CPU_MODE_STEP_ENA;  in bce_init_rxp_cpu()
4132 	cpu_reg.state = BCE_RXP_CPU_STATE;  in bce_init_rxp_cpu()
4133 	cpu_reg.state_value_clear = 0xffffff;  in bce_init_rxp_cpu()
4134 	cpu_reg.gpr0 = BCE_RXP_CPU_REG_FILE;  in bce_init_rxp_cpu()
4135 	cpu_reg.evmask = BCE_RXP_CPU_EVENT_MASK;  in bce_init_rxp_cpu()
4136 	cpu_reg.pc = BCE_RXP_CPU_PROGRAM_COUNTER;  in bce_init_rxp_cpu()
4137 	cpu_reg.inst = BCE_RXP_CPU_INSTRUCTION;  in bce_init_rxp_cpu()
4138 	cpu_reg.bp = BCE_RXP_CPU_HW_BREAKPOINT;  in bce_init_rxp_cpu()
4139 	cpu_reg.spad_base = BCE_RXP_SCRATCH;  in bce_init_rxp_cpu()
4140 	cpu_reg.mips_view_base = 0x8000000;  in bce_init_rxp_cpu()
4205 	bce_load_cpu_fw(sc, &cpu_reg, &fw);  in bce_init_rxp_cpu()
4221 	struct cpu_reg cpu_reg;  in bce_init_txp_cpu()  local
4226 	cpu_reg.mode = BCE_TXP_CPU_MODE;  in bce_init_txp_cpu()
4227 	cpu_reg.mode_value_halt = BCE_TXP_CPU_MODE_SOFT_HALT;  in bce_init_txp_cpu()
4228 	cpu_reg.mode_value_sstep = BCE_TXP_CPU_MODE_STEP_ENA;  in bce_init_txp_cpu()
4229 	cpu_reg.state = BCE_TXP_CPU_STATE;  in bce_init_txp_cpu()
4230 	cpu_reg.state_value_clear = 0xffffff;  in bce_init_txp_cpu()
4231 	cpu_reg.gpr0 = BCE_TXP_CPU_REG_FILE;  in bce_init_txp_cpu()
4232 	cpu_reg.evmask = BCE_TXP_CPU_EVENT_MASK;  in bce_init_txp_cpu()
4233 	cpu_reg.pc = BCE_TXP_CPU_PROGRAM_COUNTER;  in bce_init_txp_cpu()
4234 	cpu_reg.inst = BCE_TXP_CPU_INSTRUCTION;  in bce_init_txp_cpu()
4235 	cpu_reg.bp = BCE_TXP_CPU_HW_BREAKPOINT;  in bce_init_txp_cpu()
4236 	cpu_reg.spad_base = BCE_TXP_SCRATCH;  in bce_init_txp_cpu()
4237 	cpu_reg.mips_view_base = 0x8000000;  in bce_init_txp_cpu()
4302 	bce_load_cpu_fw(sc, &cpu_reg, &fw);  in bce_init_txp_cpu()
4303     bce_start_cpu(sc, &cpu_reg);  in bce_init_txp_cpu()
4317 	struct cpu_reg cpu_reg;  in bce_init_tpat_cpu()  local
4322 	cpu_reg.mode = BCE_TPAT_CPU_MODE;  in bce_init_tpat_cpu()
4323 	cpu_reg.mode_value_halt = BCE_TPAT_CPU_MODE_SOFT_HALT;  in bce_init_tpat_cpu()
4324 	cpu_reg.mode_value_sstep = BCE_TPAT_CPU_MODE_STEP_ENA;  in bce_init_tpat_cpu()
4325 	cpu_reg.state = BCE_TPAT_CPU_STATE;  in bce_init_tpat_cpu()
4326 	cpu_reg.state_value_clear = 0xffffff;  in bce_init_tpat_cpu()
4327 	cpu_reg.gpr0 = BCE_TPAT_CPU_REG_FILE;  in bce_init_tpat_cpu()
4328 	cpu_reg.evmask = BCE_TPAT_CPU_EVENT_MASK;  in bce_init_tpat_cpu()
4329 	cpu_reg.pc = BCE_TPAT_CPU_PROGRAM_COUNTER;  in bce_init_tpat_cpu()
4330 	cpu_reg.inst = BCE_TPAT_CPU_INSTRUCTION;  in bce_init_tpat_cpu()
4331 	cpu_reg.bp = BCE_TPAT_CPU_HW_BREAKPOINT;  in bce_init_tpat_cpu()
4332 	cpu_reg.spad_base = BCE_TPAT_SCRATCH;  in bce_init_tpat_cpu()
4333 	cpu_reg.mips_view_base = 0x8000000;  in bce_init_tpat_cpu()
4398 	bce_load_cpu_fw(sc, &cpu_reg, &fw);  in bce_init_tpat_cpu()
4399 	bce_start_cpu(sc, &cpu_reg);  in bce_init_tpat_cpu()
4413 	struct cpu_reg cpu_reg;  in bce_init_cp_cpu()  local
4418 	cpu_reg.mode = BCE_CP_CPU_MODE;  in bce_init_cp_cpu()
4419 	cpu_reg.mode_value_halt = BCE_CP_CPU_MODE_SOFT_HALT;  in bce_init_cp_cpu()
4420 	cpu_reg.mode_value_sstep = BCE_CP_CPU_MODE_STEP_ENA;  in bce_init_cp_cpu()
4421 	cpu_reg.state = BCE_CP_CPU_STATE;  in bce_init_cp_cpu()
4422 	cpu_reg.state_value_clear = 0xffffff;  in bce_init_cp_cpu()
4423 	cpu_reg.gpr0 = BCE_CP_CPU_REG_FILE;  in bce_init_cp_cpu()
4424 	cpu_reg.evmask = BCE_CP_CPU_EVENT_MASK;  in bce_init_cp_cpu()
4425 	cpu_reg.pc = BCE_CP_CPU_PROGRAM_COUNTER;  in bce_init_cp_cpu()
4426 	cpu_reg.inst = BCE_CP_CPU_INSTRUCTION;  in bce_init_cp_cpu()
4427 	cpu_reg.bp = BCE_CP_CPU_HW_BREAKPOINT;  in bce_init_cp_cpu()
4428 	cpu_reg.spad_base = BCE_CP_SCRATCH;  in bce_init_cp_cpu()
4429 	cpu_reg.mips_view_base = 0x8000000;  in bce_init_cp_cpu()
4494 	bce_load_cpu_fw(sc, &cpu_reg, &fw);  in bce_init_cp_cpu()
4495 	bce_start_cpu(sc, &cpu_reg);  in bce_init_cp_cpu()
4509 	struct cpu_reg cpu_reg;  in bce_init_com_cpu()  local
4514 	cpu_reg.mode = BCE_COM_CPU_MODE;  in bce_init_com_cpu()
4515 	cpu_reg.mode_value_halt = BCE_COM_CPU_MODE_SOFT_HALT;  in bce_init_com_cpu()
4516 	cpu_reg.mode_value_sstep = BCE_COM_CPU_MODE_STEP_ENA;  in bce_init_com_cpu()
4517 	cpu_reg.state = BCE_COM_CPU_STATE;  in bce_init_com_cpu()
4518 	cpu_reg.state_value_clear = 0xffffff;  in bce_init_com_cpu()
4519 	cpu_reg.gpr0 = BCE_COM_CPU_REG_FILE;  in bce_init_com_cpu()
4520 	cpu_reg.evmask = BCE_COM_CPU_EVENT_MASK;  in bce_init_com_cpu()
4521 	cpu_reg.pc = BCE_COM_CPU_PROGRAM_COUNTER;  in bce_init_com_cpu()
4522 	cpu_reg.inst = BCE_COM_CPU_INSTRUCTION;  in bce_init_com_cpu()
4523 	cpu_reg.bp = BCE_COM_CPU_HW_BREAKPOINT;  in bce_init_com_cpu()
4524 	cpu_reg.spad_base = BCE_COM_SCRATCH;  in bce_init_com_cpu()
4525 	cpu_reg.mips_view_base = 0x8000000;  in bce_init_com_cpu()
4590 	bce_load_cpu_fw(sc, &cpu_reg, &fw);  in bce_init_com_cpu()
4591 	bce_start_cpu(sc, &cpu_reg);  in bce_init_com_cpu()