1629 	REG_WR(sc, offset, val);  in bce_reg_wr()
1744 		REG_WR(sc, BCE_CTX_CTX_CTRL, (offset | BCE_CTX_CTX_CTRL_READ_REQ));  in bce_ctx_rd()
1760 		REG_WR(sc, BCE_CTX_DATA_ADR, offset);  in bce_ctx_rd()
1794 		REG_WR(sc, BCE_CTX_CTX_DATA, ctx_val);  in bce_ctx_wr()
1795 		REG_WR(sc, BCE_CTX_CTX_CTRL, (offset | BCE_CTX_CTX_CTRL_WRITE_REQ));  in bce_ctx_wr()
1810 		REG_WR(sc, BCE_CTX_DATA_ADR, offset);  in bce_ctx_wr()
1811 		REG_WR(sc, BCE_CTX_DATA, ctx_val);  in bce_ctx_wr()
1846 		REG_WR(sc, BCE_EMAC_MDIO_MODE, val);  in bce_miibus_read_reg()
1855 	REG_WR(sc, BCE_EMAC_MDIO_COMM, val);  in bce_miibus_read_reg()
1883 		REG_WR(sc, BCE_EMAC_MDIO_MODE, val);  in bce_miibus_read_reg()
1926 		REG_WR(sc, BCE_EMAC_MDIO_MODE, val1);  in bce_miibus_write_reg()
1935 	REG_WR(sc, BCE_EMAC_MDIO_COMM, val1);  in bce_miibus_write_reg()
1955 		REG_WR(sc, BCE_EMAC_MDIO_MODE, val1);  in bce_miibus_write_reg()
2044 	REG_WR(sc, BCE_EMAC_MODE, val);  in bce_miibus_statchg()
2095 	REG_WR(sc, BCE_NVM_SW_ARB, BCE_NVM_SW_ARB_ARB_REQ_SET2);  in bce_acquire_nvram_lock()
2134 	REG_WR(sc, BCE_NVM_SW_ARB, BCE_NVM_SW_ARB_ARB_REQ_CLR2);  in bce_release_nvram_lock()
2171 	REG_WR(sc, BCE_MISC_CFG, val | BCE_MISC_CFG_NVM_WR_EN_PCI);  in bce_enable_nvram_write()
2176 		REG_WR(sc, BCE_NVM_COMMAND, BCE_NVM_COMMAND_DONE);  in bce_enable_nvram_write()
2177 		REG_WR(sc, BCE_NVM_COMMAND,	BCE_NVM_COMMAND_WREN | BCE_NVM_COMMAND_DOIT);  in bce_enable_nvram_write()
2214 	REG_WR(sc, BCE_MISC_CFG, val & ~BCE_MISC_CFG_NVM_WR_EN);  in bce_disable_nvram_write()
2239 	REG_WR(sc, BCE_NVM_ACCESS_ENABLE, val |  in bce_enable_nvram_access()
2263 	REG_WR(sc, BCE_NVM_ACCESS_ENABLE, val &  in bce_disable_nvram_access()
2299 	REG_WR(sc, BCE_NVM_COMMAND, BCE_NVM_COMMAND_DONE);  in bce_nvram_erase_page()
2300 	REG_WR(sc, BCE_NVM_ADDR, offset & BCE_NVM_ADDR_NVM_ADDR_VALUE);  in bce_nvram_erase_page()
2301 	REG_WR(sc, BCE_NVM_COMMAND, cmd);  in bce_nvram_erase_page()
2357 	REG_WR(sc, BCE_NVM_COMMAND, BCE_NVM_COMMAND_DONE);  in bce_nvram_read_dword()
2358 	REG_WR(sc, BCE_NVM_ADDR, offset & BCE_NVM_ADDR_NVM_ADDR_VALUE);  in bce_nvram_read_dword()
2359 	REG_WR(sc, BCE_NVM_COMMAND, cmd);  in bce_nvram_read_dword()
2422 	REG_WR(sc, BCE_NVM_COMMAND, BCE_NVM_COMMAND_DONE);  in bce_nvram_write_dword()
2425 	REG_WR(sc, BCE_NVM_WRITE, val32);  in bce_nvram_write_dword()
2426 	REG_WR(sc, BCE_NVM_ADDR, offset & BCE_NVM_ADDR_NVM_ADDR_VALUE);  in bce_nvram_write_dword()
2427 	REG_WR(sc, BCE_NVM_COMMAND, cmd);  in bce_nvram_write_dword()
2521 				REG_WR(sc, BCE_NVM_CFG1, flash->config1);  in bce_init_nvram()
2522 				REG_WR(sc, BCE_NVM_CFG2, flash->config2);  in bce_init_nvram()
2523 				REG_WR(sc, BCE_NVM_CFG3, flash->config3);  in bce_init_nvram()
2524 				REG_WR(sc, BCE_NVM_WRITE1, flash->write1);  in bce_init_nvram()
3934 		REG_WR(sc, BCE_RV2P_INSTR_HIGH, *rv2p_code);  in bce_load_rv2p_fw()
3936 		REG_WR(sc, BCE_RV2P_INSTR_LOW, *rv2p_code);  in bce_load_rv2p_fw()
3941 			REG_WR(sc, BCE_RV2P_PROC1_ADDR_CMD, val);  in bce_load_rv2p_fw()
3945 			REG_WR(sc, BCE_RV2P_PROC2_ADDR_CMD, val);  in bce_load_rv2p_fw()
3951 		REG_WR(sc, BCE_RV2P_COMMAND, BCE_RV2P_COMMAND_PROC1_RESET);  in bce_load_rv2p_fw()
3954 		REG_WR(sc, BCE_RV2P_COMMAND, BCE_RV2P_COMMAND_PROC2_RESET);  in bce_load_rv2p_fw()
4668 		REG_WR(sc, BCE_CTX_COMMAND, val);  in bce_init_ctx()
4686 			REG_WR(sc, BCE_CTX_HOST_PAGE_TBL_DATA0,  in bce_init_ctx()
4689 			REG_WR(sc, BCE_CTX_HOST_PAGE_TBL_DATA1,  in bce_init_ctx()
4691 			REG_WR(sc, BCE_CTX_HOST_PAGE_TBL_CTRL, i |  in bce_init_ctx()
4722 			REG_WR(sc, BCE_CTX_VIRT_ADDR, 0);  in bce_init_ctx()
4723 			REG_WR(sc, BCE_CTX_PAGE_TBL, vcid_addr);  in bce_init_ctx()
4729 			REG_WR(sc, BCE_CTX_VIRT_ADDR, vcid_addr);  in bce_init_ctx()
4730 			REG_WR(sc, BCE_CTX_PAGE_TBL, vcid_addr);  in bce_init_ctx()
4800 	REG_WR(sc, BCE_EMAC_MAC_MATCH0, val);  in bce_set_mac_addr()
4805 	REG_WR(sc, BCE_EMAC_MAC_MATCH1, val);  in bce_set_mac_addr()
4830 	REG_WR(sc, BCE_MISC_ENABLE_CLR_BITS, BCE_MISC_ENABLE_CLR_DEFAULT);  in bce_stop()
4877 	REG_WR(sc, BCE_MISC_ENABLE_CLR_BITS,  in bce_reset()
4889 		REG_WR(sc, BCE_MISC_NEW_CORE_CTL, val);  in bce_reset()
4909 		REG_WR(sc, BCE_MISC_COMMAND, BCE_MISC_COMMAND_SW_RESET);  in bce_reset()
4921 		REG_WR(sc, BCE_PCICFG_MISC_CONFIG, val);  in bce_reset()
4969 		REG_WR(sc, BCE_EMAC_MODE, val);  in bce_reset()
5014 	REG_WR(sc, BCE_DMA_CONFIG, val);  in bce_chipinit()
5017 	REG_WR(sc, BCE_MISC_ENABLE_SET_BITS,  in bce_chipinit()
5032 		REG_WR(sc, BCE_RPM_MGMT_PKT_CTRL, val);  in bce_chipinit()
5051 	REG_WR(sc, BCE_MQ_CONFIG, val);  in bce_chipinit()
5054 	REG_WR(sc, BCE_MQ_KNL_BYP_WIND_START, val);  in bce_chipinit()
5055 	REG_WR(sc, BCE_MQ_KNL_WIND_END, val);  in bce_chipinit()
5059 	REG_WR(sc, BCE_RV2P_CONFIG, val);  in bce_chipinit()
5065 	REG_WR(sc, BCE_TBDR_CONFIG, val);  in bce_chipinit()
5097 	REG_WR(sc, BCE_EMAC_BACKOFF_SEED, val);  in bce_blockinit()
5103 	REG_WR(sc, BCE_EMAC_ATTENTION_ENA, BCE_EMAC_ATTENTION_ENA_LINK);  in bce_blockinit()
5106 	REG_WR(sc, BCE_HC_STATUS_ADDR_L,  in bce_blockinit()
5108 	REG_WR(sc, BCE_HC_STATUS_ADDR_H,  in bce_blockinit()
5112 	REG_WR(sc, BCE_HC_STATISTICS_ADDR_L,  in bce_blockinit()
5114 	REG_WR(sc, BCE_HC_STATISTICS_ADDR_H,  in bce_blockinit()
5123 	REG_WR(sc, BCE_HC_TX_QUICK_CONS_TRIP,  in bce_blockinit()
5126 	REG_WR(sc, BCE_HC_RX_QUICK_CONS_TRIP,  in bce_blockinit()
5129 	REG_WR(sc, BCE_HC_TX_TICKS,  in bce_blockinit()
5131 	REG_WR(sc, BCE_HC_RX_TICKS,  in bce_blockinit()
5133 	REG_WR(sc, BCE_HC_STATS_TICKS, sc->bce_stats_ticks & 0xffff00);  in bce_blockinit()
5134 	REG_WR(sc, BCE_HC_STAT_COLLECT_TICKS, 0xbb8);  /* 3ms */  in bce_blockinit()
5136 	REG_WR(sc, BCE_HC_COMP_PROD_TRIP, 0);  in bce_blockinit()
5137 	REG_WR(sc, BCE_HC_COM_TICKS, 0);  in bce_blockinit()
5138 	REG_WR(sc, BCE_HC_CMD_TICKS, 0);  in bce_blockinit()
5150 		REG_WR(sc, BCE_HC_MSIX_BIT_VECTOR, BCE_HC_MSIX_BIT_VECTOR_VAL);  in bce_blockinit()
5152 		REG_WR(sc, base, BCE_HC_SB_CONFIG_1_TX_TMR_MODE |  in bce_blockinit()
5155 		REG_WR(sc, base + BCE_HC_TX_QUICK_CONS_TRIP_OFF,  in bce_blockinit()
5159 		REG_WR(sc, base + BCE_HC_TX_TICKS_OFF,  in bce_blockinit()
5178 	REG_WR(sc, BCE_HC_CONFIG, val);  in bce_blockinit()
5181 	REG_WR(sc, BCE_HC_COMMAND, BCE_HC_COMMAND_CLR_STAT_NOW);  in bce_blockinit()
5205 		REG_WR(sc, BCE_MISC_NEW_CORE_CTL, val);  in bce_blockinit()
5213 	REG_WR(sc, BCE_HC_ATTN_BITS_ENABLE, STATUS_ATTN_BITS_LINK_STATE);  in bce_blockinit()
5222 		REG_WR(sc, BCE_RPM_MGMT_PKT_CTRL, val);  in bce_blockinit()
5227 		REG_WR(sc, BCE_MISC_ENABLE_SET_BITS,  in bce_blockinit()
5230 		REG_WR(sc, BCE_MISC_ENABLE_SET_BITS,  in bce_blockinit()
5672 		REG_WR(sc, BCE_MQ_MAP_L2_5, val | BCE_MQ_MAP_L2_5_ARM);  in bce_init_rx_context()
5788 	REG_WR(sc, MB_GET_CID_ADDR(RX_CID) + BCE_L2MQ_RX_HOST_BSEQ, prod_bseq);  in bce_fill_rx_chain()
5882 		REG_WR(sc, BCE_MQ_MAP_L2_3, BCE_MQ_MAP_L2_3_DEFAULT);  in bce_init_pg_chain()
6330 			REG_WR(sc, BCE_PCICFG_STATUS_BIT_SET_CMD,  in bce_phy_intr()
6335 			REG_WR(sc, BCE_PCICFG_STATUS_BIT_CLEAR_CMD,  in bce_phy_intr()
6365 	REG_WR(sc, BCE_EMAC_STATUS, BCE_EMAC_STATUS_LINK_CHANGE);  in bce_phy_intr()
6888 	REG_WR(sc, BCE_PCICFG_INT_ACK_CMD, BCE_PCICFG_INT_ACK_CMD_MASK_INT);  in bce_disable_intr()
6905 	REG_WR(sc, BCE_PCICFG_INT_ACK_CMD,  in bce_enable_intr()
6909 	REG_WR(sc, BCE_PCICFG_INT_ACK_CMD,  in bce_enable_intr()
6914 		REG_WR(sc, BCE_HC_COMMAND, sc->hc_command | BCE_HC_COMMAND_COAL_NOW);  in bce_enable_intr()
6996 		REG_WR(sc, BCE_EMAC_RX_MTU_SIZE,  in bce_init_locked()
7000 		REG_WR(sc, BCE_EMAC_RX_MTU_SIZE, ether_mtu);  in bce_init_locked()
7057 	REG_WR(sc, BCE_MISC_ENABLE_SET_BITS, BCE_MISC_ENABLE_DEFAULT);  in bce_mgmt_init_locked()
7394 	REG_WR(sc, MB_GET_CID_ADDR(TX_CID) +  in bce_tx_encap()
7746 	REG_WR(sc, BCE_EMAC_RX_STATUS, status);  in bce_watchdog()
7799 	REG_WR(sc, BCE_PCICFG_INT_ACK_CMD,  in bce_intr()
7825 			REG_WR(sc, BCE_HC_COMMAND, sc->hc_command |  in bce_intr()
7954 			REG_WR(sc, BCE_EMAC_MULTICAST_HASH0 + (i * 4),  in bce_set_rx_mode()
7964 			REG_WR(sc, BCE_EMAC_MULTICAST_HASH0 + (i * 4), hashes[i]);  in bce_set_rx_mode()
7975 		REG_WR(sc, BCE_EMAC_RX_MODE, rx_mode);  in bce_set_rx_mode()
7979 	REG_WR(sc, BCE_RPM_SORT_USER0, 0x0);  in bce_set_rx_mode()
7980 	REG_WR(sc, BCE_RPM_SORT_USER0, sort_mode);  in bce_set_rx_mode()
7981 	REG_WR(sc, BCE_RPM_SORT_USER0, sort_mode | BCE_RPM_SORT_USER0_ENA);  in bce_set_rx_mode()
8530 		REG_WR(sc, BCE_HC_COMMAND, BCE_HC_COMMAND_CLR_STAT_NOW);  in bce_sysctl_stats_clear()
9507 	REG_WR(sc, BCE_MISC_COMMAND, val);  in bce_freeze_controller()
9523 	REG_WR(sc, BCE_MISC_COMMAND, val);  in bce_unfreeze_controller()
10104 	REG_WR(sc, BCE_HC_STAT_GEN_SEL_0, val);  in bce_dump_ftqs()
10110 	REG_WR(sc, BCE_HC_STAT_GEN_SEL_1, val);  in bce_dump_ftqs()
10116 	REG_WR(sc, BCE_HC_STAT_GEN_SEL_2, val);  in bce_dump_ftqs()
10122 	REG_WR(sc, BCE_HC_STAT_GEN_SEL_3, val);  in bce_dump_ftqs()
10277 	REG_WR(sc, BCE_HC_STAT_GEN_SEL_0, val);  in bce_dump_ftqs()